US2017018513A1PendingUtilityA1
Semiconductor package including an antenna formed in a groove within a sealing element
Est. expiryJul 7, 2031(~4.9 yrs left)· nominal 20-yr term from priority
H10P 54/00H10W 90/754H10W 90/732H10W 90/724H10W 90/00H10W 74/01H10W 74/00H10W 72/9413H10W 72/884H10W 72/29H10W 44/251H10W 44/248H10W 44/209H10W 74/127H10W 74/019H10W 74/016H10W 74/014H10W 72/0198H10W 70/685H10W 70/635H10W 70/614H10W 70/095H10W 70/093H10W 70/65H10W 70/09H10W 70/05H10W 20/42H10W 72/00H10W 44/20H10W 70/60H01L 23/3142H01L 21/4853H01L 21/486H01L 23/66H01L 21/565H01L 23/49822H01L 2223/6683H01L 21/4857H01L 23/49838H01L 21/78H01L 2223/6677H01L 23/49827H01L 2223/6616H01Q 1/2283H01Q 1/24H05K 2203/061H05K 1/185
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Claims
Abstract
There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part or the substrate part and electrically connected to the semiconductor chip.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor package comprising:
a semiconductor chip; a sealing layer formed on, and configured to seal, the semiconductor chip, wherein the sealing layer contacts and seals top and side surfaces of the semiconductor chip; a substrate layer disposed on at least one surface of the sealing layer; an antenna disposed on the sealing layer and electrically connected to the semiconductor chip; and a connection via electrically connecting the antenna to a lower surface of the sealing layer, wherein the substrate layer comprises a first material and the sealing layer comprises a second material different from the first material.
2 . The semiconductor package of claim 1 , wherein the antenna and the semiconductor chip are electrically connected to each other through the connection via.
3 . The semiconductor package of claim 1 , wherein the substrate layer includes:
an upper substrate disposed on an upper surface of the sealing layer; and a lower substrate disposed on the lower surface of the sealing layer.
4 . The semiconductor package of claim 3 , wherein the antenna is formed on an outer surface of the upper substrate.
5 . The semiconductor package of claim 4 , wherein the upper substrate is a multi-layer substrate, and
the antenna includes a plurality of radiators disposed on several layers of the upper substrate.
6 . The semiconductor package of claim 1 , wherein the substrate layer has fine circuit patterns formed in an inner portion thereof through a semiconductor manufacturing process.
7 . The semiconductor package of claim 1 , wherein the semiconductor chip transceives a high frequency in a millimeter wave band through the antenna.
8 . A semiconductor package, comprising:
a sealing layer disposed between an upper multi-layered substrate and a multi-layered lower substrate; a semiconductor chip embedded within the sealing layer; an antenna disposed on the upper multi-layered substrate; and a connection via electrically connecting the antenna, the upper multi-layered substrate, the semiconductor chip, and the lower multi-layered substrate.
9 . The semiconductor package of claim 8 , wherein the antenna comprises a plurality of radiators disposed on layers of the upper multi-layered substrate.
10 . The semiconductor package of claim 8 , wherein circuit patterns are disposed on a layer of the lower multi-layered substrate.
11 . The semiconductor package of claim 8 , wherein the connection via is laterally offset from the semiconductor chip.
12 . A millimeter wave band device comprising the semiconductor package of claim 8 .Join the waitlist — get patent alerts
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