Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit

Abstract

An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

1 . An integrated circuit, comprising:
 a substrate;   a metal oxide semiconductor (MOS) transistor comprising:   a gate region buried in a trench of the substrate and emerging on a top face of the substrate, said gate region surrounded by a dielectric region covering internal walls of the trench;   a source region and a drain region situated respectively in the substrate on opposite sides of the trench in a vicinity of said top face;   said dielectric region having an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions, and a lower dielectric zone, which is less thick than the upper dielectric zone, situated between a lower part of the gate region and the substrate.   
     
     
         2 . The integrated circuit according to  claim 1 , wherein the gate region comprises a gate setback zone between the lower part and the upper part of the gate region. 
     
     
         3 . The integrated circuit according to  claim 1 , wherein the dielectric region comprises a dielectric setback zone between the lower dielectric zone and the upper dielectric zone. 
     
     
         4 . A method for fabricating a metal oxide semiconductor (MOS) transistor, comprising:
 forming a gate region buried in a trench of the substrate, said gate region emerging on a top face of the substrate;   forming a source region and a drain region situated in the substrate on opposite sides of the trench in a vicinity of said top face;   forming a dielectric region covering internal walls of the trench surrounding the gate region and having an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions, and a lower dielectric zone, less thick than the upper dielectric zone, situated between a lower part of the gate region and the substrate.   
     
     
         5 . The method according to  claim 4 , wherein forming the gate region comprises forming a gate setback zone between the lower part and the upper part of the gate region. 
     
     
         6 . The method according to  claim 5 , wherein forming the dielectric region and gate region comprise:
 forming a first dielectric layer covering the internal wall of the trench;   forming a sacrificial gate region covering the first dielectric layer and filling the trench;   partially removing the sacrificial gate region so as to obtain the lower part of the gate region surrounded by the lower dielectric zone;   forming a second dielectric layer covering the first dielectric layer and the lower part of the gate region;   removing the portion of the second dielectric layer covering the lower part of the gate region so as to obtain the upper dielectric zone; and   forming the gate region comprising the upper part separated from the lower part by the gate setback zone and surrounded by the upper and lower dielectric zones.   
     
     
         7 . The method according to  claim 4 , wherein forming the dielectric region comprises a dielectric setback zone between the lower dielectric zone and the upper dielectric zone. 
     
     
         8 . The method according to  claim 7 , wherein forming the dielectric region and the gate region comprises:
 partially etching an isolation trench leaving a first dielectric layer remaining on lateral walls;   partially etching the underlying substrate so as to obtain said trench;   forming on the first dielectric layer and on the walls of the lower part of the trench a second dielectric layer so as to obtain said dielectric setback region; and   filling the trench with a gate material.   
     
     
         9 . A integrated circuit, comprising:
 a substrate having a top surface;   a trench extending into the substrate from the top surface, said trench having sidewalls and a bottom;   a dielectric layer covering said sidewalls and bottom;   a gate electrode filling said trench and separated from the substrate by said dielectric layer;   source and drain regions in said substrate on opposite sides of the trench;   wherein said dielectric layer covering said sidewalls has a first sidewall thickness in an upper portion of said trench and a second sidewall thickness in a lower portion of said trench, said second sidewall thickness being greater than said first sidewall thickness.   
     
     
         10 . The integrated circuit of  claim 9 , further comprising a gate setback zone at a depth of the trench where the thickness of the dielectric layer changes from the first sidewall thickness to the second sidewall thickness. 
     
     
         11 . The integrated circuit of  claim 10 , wherein the gate setback zone defines a step change in a lateral width of the gate electrode. 
     
     
         12 . The integrated circuit of  claim 9 , further comprising a dielectric setback zone at a depth of the trench where the thickness of the dielectric layer changes from the first sidewall thickness to the second sidewall thickness. 
     
     
         13 . The integrated circuit of  claim 12 , wherein the dielectric setback zone defines a step change in a lateral width of the dielectric layer thickness. 
     
     
         14 . A method, comprising:
 forming a trench in a top surface of a substrate;   lining the trench with a first layer of dielectric material;   filling a bottom of the trench with a lower gate material;   lining the trench with a second layer of dielectric material;   filling a top of the trench with an upper gate material, the upper and lower gate materials forming a gate electrode separated from the substrate by the first layer of dielectric material at a lower gate region of the gate electrode and separated from the substrate by the first and second layers of dielectric material at an upper gate region of the gate electrode; and   forming source and drain regions on opposite sides of the trench.   
     
     
         15 . A method, comprising;
 forming a trench in a top surface of a substrate;   filling the trench with a dielectric material;   etching an opening in the dielectric material leaving an upper insulating sidewall made from the dielectric material;   extending said opening into the trench to form an extended trench;   lining sidewalls and a bottom of the extended trench with a dielectric liner;   filling the extended trench with a gate material to form a gate electrode separated from the substrate by an insulating layer having a first thickness and made from at least the upper insulating sidewall in an upper region and having a second thickness less than the first thickness and made from the dielectric liner in a lower region; and   forming source and drain regions on opposite sides of the trench.