US2017012025A1PendingUtilityA1

Semiconductor packages and methods of manufacturing semiconductor packages

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Mar 30, 2012Filed: Sep 23, 2016Published: Jan 12, 2017
Est. expiryMar 30, 2032(~5.7 yrs left)· nominal 20-yr term from priority
H10P 74/207H10P 74/20H10W 90/755H10W 90/754H10W 90/724H10W 90/291H10W 90/284H10W 90/20H10W 74/019H10W 74/15H10W 74/00H10W 72/07507H10W 72/5449H10W 72/932H10W 72/926H10W 72/884H10W 72/877H10W 72/859H10W 72/0198H10W 72/00H10W 70/63H10W 74/117H10W 74/016H10W 74/014H10W 72/50H10W 72/20H10W 70/685H10W 70/093H10W 70/65H10W 70/05H10W 90/00H10W 70/60H01L 25/0657H01L 21/4857H01L 2225/06596H01L 2225/06517H01L 25/50H01L 22/14H01L 24/73H01L 21/4853H01L 24/16H01L 23/49838H01L 2225/0651H01L 2924/3511H01L 2224/73207H01L 2225/06555H01L 24/45H01L 2225/06582H01L 23/49822H01L 2924/37001H01L 2224/16227H01L 2224/48157
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Claims

Abstract

A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of manufacturing a semiconductor package, comprising:
 mounting a first semiconductor chip on an upper surface of a mounting substrate to form a preliminary package;   testing the preliminary package;   stacking a unit package on the first semiconductor chip, the unit package including a package substrate and a second semiconductor chip mounted thereon;   connecting bonding pads of the mounting substrate and connection pads of the unit package using a plurality of bonding wires to electrically connect the first and second semiconductor chips to each other; and   forming a molding member on the mounting substrate to cover the first semiconductor chip and the unit package.   
     
     
         2 . The method of  claim 1 , wherein if the preliminary package passes the testing, the stacking a unit package on the first semiconductor chip is performed. 
     
     
         3 . The method of  claim 1 , wherein the stacking a unit package on the first semiconductor chip comprises:
 adhering a plurality of the preliminary packages on a carrier frame; and   stacking a plurality of the unit packages on the preliminary packages, respectively.   
     
     
         4 . The method of  claim 3 , wherein the molding member covers at least a side portion of the mounting substrate. 
     
     
         5 . The method of  claim 1 , wherein the bonding pads of the mounting substrate comprises data signal_bonding pads and control signal_bonding pads, and the data signal_bonding pads and the control signal_bonding pads are arranged along a side portion of the mounting substrate.

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