Semiconductor memory device and operating method thereof

Abstract

A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

1 - 11 . (canceled) 
     
     
         12 . A method of operating a semiconductor memory device, the method comprising:
 performing a first program operation to increase threshold voltages of first, second and third memory cells having first, second and third target levels different from one another, respectively, to sub-levels lower than the different target levels;   performing a first verify operation to verify the first memory cells by using a first verify voltage;   performing a second verify operation to verify the second memory cells by using a second verify voltage;   performing a third verify operation to verify the third memory cells by using a third verify voltage;   performing a second program operation to divide the threshold voltages of the first to third memory cells; and   performing a third program operation to program the first, second and third memory cells, wherein the threshold voltages of the first, second and third memory cells are greater than the first, second and third target levels, respectively.   
     
     
         13 . The method of  claim 12 , wherein the second target level is higher than the first target level, and the third target level is higher than the second target level. 
     
     
         14 . The method of  claim 12 , wherein the performing of the first program operation comprises:
 applying a first program pulse once to a word line coupled to the first to third memory cells without performing a verify operation.   
     
     
         15 . The method of  claim 12 , wherein the first to third verify voltages different from each other are set to be greater than a lowest voltage, among the threshold voltages of the first to third memory cells, respectively. 
     
     
         16 . The method of  claim 12 , wherein the performing of the second program operation comprises:
 selecting the first to third memory cells and applying a second program pulse to a selected word line; and   selecting the second and third memory cells and applying a third program pulse to the selected word line.   
     
     
         17 . The method of  claim 16 , wherein each of the second and third program pulses is applied to the selected word line once. 
     
     
         18 . The method of  claim 16 , wherein the third program pulse is set to be higher than the second program pulse. 
     
     
         19 . The method of  claim 16 , wherein the performing of the second program operation further comprises:
 selecting the third memory cells and applying a fourth program pulse to the selected word line, after the applying of the third program pulse to the selected word line.   
     
     
         20 . The method of  claim 12 , wherein the third program operation is performed on each of the first to third memory cells by an Incremental Step Pulse Program method. 
     
     
         21 . A method of operating a semiconductor memory device, the method comprising:
 defining a plurality of memory cell groups each including memory cells having different target levels;   performing a first program operation on the plurality of memory cell groups to have different threshold voltage distributions;   verifying the memory cells having the different target levels by using different verify voltages;   performing a second program operation to divide the memory cells into different threshold voltage distributions; and   performing a third program operation to increase threshold voltages of the memory cells to the different target levels, respectively.   
     
     
         22 . The method of  claim 21 , wherein the performing of the first program operation comprises:
 sequentially applying different program pulses to selected word lines of the memory cell groups.   
     
     
         23 . The method of  claim 21 , wherein the different verify voltages are set to be higher than a lowest voltage, among threshold voltages of memory cells to be verified by each of the different verify voltages. 
     
     
         24 . The method of  claim 21 , wherein the performing of the second program operation comprises:
 selecting memory cells have the same target level, among the memory cells; and   applying a program pulse to a word line coupled to selected memory cells without performing a verify operation.   
     
     
         25 . The method of  claim 21 , wherein the third program operation is performed by using an Incremental Step Pulse Program (ISPP) scheme. 
     
     
         26 - 31 . (canceled) 
     
     
         32 . A method of operating a semiconductor memory device, the method comprising:
 programming first memory cells having a first program target level and second memory cells having a second program target level different from the first program target level to have a first threshold voltage distribution by using a first program pulse;   verifying the first memory cells and the second memory cells by using first and second verify voltages different from each other, respectively;   programming the first memory cells and the second memory cells to have second and third threshold voltage distributions different from each other, respectively, by using a second program pulse; and   programming the first memory cells and the second memory cells to increase threshold voltages thereof to the first and second program target levels, respectively.   
     
     
         33 . The method of  claim 32 , wherein a level of the second program pulse is set by performing an operation using a level of the first program pulse, a level of a highest threshold voltage in the first threshold voltage distribution, and a level of a highest threshold voltage in the second and third threshold voltage distributions.