Programmable High-Speed I/O Interface

Abstract

Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application.

What is claimed is: 
     
         1 . A selectively-configurable I/O interface, comprising:
 a plurality of buffers;   a first pad selectively-coupled to at least one buffer from among the plurality of buffers;   a second pad selectively-coupled to at least one buffer from among the plurality of buffers; and   programmable logic to enable the selectively-configurable I/O interface to be configured in first and second configurations,   wherein when in the first configuration the selectively-configurable I/O interface is configured to receive a single-ended signal at the first pad and buffer the signal in a buffer from among the plurality of buffers coupled to the first pad,   and wherein when in the second configuration the selectively-configurable I/O interface is configured to receive a differential signal at the first and second pads and buffer the differential signal in a buffer from among the plurality of buffers that is coupled to the first and second pads.