US2017004788A1PendingUtilityA1

Liquid crystal display device and electronic device including the liquid crystal display device

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Assignee: SEMICONDUCTOR ENERGY LABPriority: Oct 16, 2009Filed: Sep 13, 2016Published: Jan 5, 2017
Est. expiryOct 16, 2029(~3.2 yrs left)· nominal 20-yr term from priority
Inventors:Shunpei YamazakiRyo ArasawaJun KoyamaMasashi TsubukuKosei Noda
H10P 95/90H10P 50/69H10P 14/69215H10P 14/6329H10P 14/3434H10P 14/22G02F 2202/10G09G 3/3614G09G 2330/021G02F 1/13439G09G 3/3648G02F 2201/123G02F 1/133553G09G 3/3677G09G 2310/0286G02F 1/1368G09G 2300/08G09G 2310/08H10D 30/6755H10D 62/10H10D 86/60H10D 99/00H10D 86/481H10D 86/423H10D 64/512H10D 64/62H10D 62/80H10D 30/6734H01L 27/1225
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Claims

Abstract

In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×10 14 /cm 3 .

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A display device comprising:
 a transistor comprising a source, a drain and a channel formation region, the channel formation region comprising an oxide semiconductor;   a pixel electrode electrically connected to the source or the drain of the transistor; and   a liquid crystal material adjacent to the pixel electrode,   wherein a specific resistance of the liquid crystal material measured at 20° C. is 1×10 12  Ω·cm or more.   
     
     
         3 . A display device comprising:
 a transistor comprising a source, a drain and a channel formation region, the channel formation region comprising an oxide semiconductor; and   a pixel electrode electrically connected to the source or the drain of the transistor,   wherein an energy gap of the oxide semiconductor is 2 eV or more, and   wherein a current per micrometer of a channel width of the channel formation region is 1×10 −17  A or less.   
     
     
         4 . A display device comprising a plurality of pixels in a display portion and configured to perform display in a plurality of frame periods, each of the plurality of pixels comprising:
 a transistor comprising a source, a drain and a channel formation region, the channel formation region comprising an oxide semiconductor; and   a pixel electrode electrically connected to the source or the drain of the transistor,   wherein each of the plurality of frame periods includes a writing period and a holding period,   wherein the holding period is variable, and   wherein the pixel electrode is a reflective electrode.   
     
     
         5 . A display device comprising a plurality of pixels in a display portion and configured to perform display in a plurality of frame periods, each of the plurality of pixels comprising:
 a transistor comprising a source, a drain and a channel formation region, the channel formation region comprising an oxide semiconductor; and   a pixel electrode electrically connected to the source or the drain of the transistor,   wherein each of the plurality of frame periods includes a writing period and a holding period,   wherein the holding period is within a range such that an image burn-in does not occur, and   wherein the pixel electrode is a reflective electrode.   
     
     
         6 . A display device comprising a plurality of pixels in a display portion and configured to perform display in a plurality of frame periods, each of the plurality of pixels comprising:
 a transistor comprising a source, a drain and a channel formation region, the channel formation region comprising an oxide semiconductor; and   a pixel electrode electrically connected to the source or the drain of the transistor,   wherein each of the plurality of frame periods includes a writing period and a holding period,   wherein the holding period is at least 10 seconds, and   wherein the pixel electrode is a reflective electrode.   
     
     
         7 . A display device comprising:
 a transistor comprising a source, a drain and a channel formation region, the channel formation region comprising an oxide semiconductor; and   a pixel electrode electrically connected to the source or the drain of the transistor,   wherein a frequency of signal writing of a still image is lower than that of a moving image.   
     
     
         8 . The display device according to  claim 2 , wherein the oxide semiconductor includes indium. 
     
     
         9 . The display device according to  claim 3 , wherein the oxide semiconductor includes indium. 
     
     
         10 . The display device according to  claim 4 , wherein the oxide semiconductor includes indium. 
     
     
         11 . The display device according to  claim 5 , wherein the oxide semiconductor includes indium. 
     
     
         12 . The display device according to  claim 6 , wherein the oxide semiconductor includes indium. 
     
     
         13 . The display device according to  claim 7 , wherein the oxide semiconductor includes indium. 
     
     
         14 . The display device according to  claim 2 , wherein the oxide semiconductor includes a microcrystalline portion with a grain diameter of 1 nm to 20 nm. 
     
     
         15 . The display device according to  claim 3 , wherein the oxide semiconductor includes a microcrystalline portion with a grain diameter of 1 nm to 20 nm. 
     
     
         16 . The display device according to  claim 4 , wherein the oxide semiconductor includes a microcrystalline portion with a grain diameter of 1 nm to 20 nm. 
     
     
         17 . The display device according to  claim 5 , wherein the oxide semiconductor includes a microcrystalline portion with a grain diameter of 1 nm to 20 nm. 
     
     
         18 . The display device according to  claim 6 , wherein the oxide semiconductor includes a microcrystalline portion with a grain diameter of 1 nm to 20 nm. 
     
     
         19 . The display device according to  claim 7 , wherein the oxide semiconductor includes a microcrystalline portion with a grain diameter of 1 nm to 20 nm. 
     
     
         20 . The display device according to  claim 3 , wherein the display device is a liquid crystal display device, an electroluminescent display device, or a display device using electronic ink. 
     
     
         21 . The display device according to  claim 4 , wherein the display device is a liquid crystal display device, an electroluminescent display device, or a display device using electronic ink. 
     
     
         22 . The display device according to  claim 5 , wherein the display device is a liquid crystal display device, an electroluminescent display device, or a display device using electronic ink. 
     
     
         23 . The display device according to  claim 6 , wherein the display device is a liquid crystal display device, an electroluminescent display device, or a display device using electronic ink. 
     
     
         24 . The display device according to  claim 7 , wherein the display device is a liquid crystal display device, an electroluminescent display device, or a display device using electronic ink. 
     
     
         25 . The display device according to  claim 2 ,
 wherein an energy gap of the oxide semiconductor is 2 eV or more, and   wherein a current per micrometer of a channel width of the channel formation region is 1×10 −17  A or less.   
     
     
         26 . The display device according to  claim 4 ,
 wherein an energy gap of the oxide semiconductor is 2 eV or more, and   wherein a current per micrometer of a channel width of the channel formation region is 1×10 −17  A or less.   
     
     
         27 . The display device according to  claim 5 ,
 wherein an energy gap of the oxide semiconductor is 2 eV or more, and   wherein a current per micrometer of a channel width of the channel formation region is 1×10 −17  A or less.   
     
     
         28 . The display device according to  claim 6 ,
 wherein an energy gap of the oxide semiconductor is 2 eV or more, and   wherein a current per micrometer of a channel width of the channel formation region is 1×10 −17  A or less.   
     
     
         29 . The display device according to  claim 7 ,
 wherein an energy gap of the oxide semiconductor is 2 eV or more, and   wherein a current per micrometer of a channel width of the channel formation region is 1×10 −17  A or less.   
     
     
         30 . The display device according to  claim 2 , wherein the pixel electrode is a reflective electrode. 
     
     
         31 . The display device according to  claim 3 , wherein the pixel electrode is a reflective electrode. 
     
     
         32 . The display device according to  claim 7 , wherein the pixel electrode is a reflective electrode. 
     
     
         33 . The display device according to  claim 4 , wherein the pixel electrode includes at least one selected from a group consisting of tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, titanium, platinum, aluminum, copper, and silver. 
     
     
         34 . The display device according to  claim 5 , wherein the pixel electrode includes at least one selected from a group consisting of tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, titanium, platinum, aluminum, copper, and silver. 
     
     
         35 . The display device according to  claim 6 , wherein the pixel electrode includes at least one selected from a group consisting of tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium, cobalt, nickel, titanium, platinum, aluminum, copper, and silver. 
     
     
         36 . The display device according to  claim 3 , further comprising a liquid crystal layer,
 wherein the liquid crystal layer comprises a twisted nematic mode.   
     
     
         37 . The display device according to  claim 6 , further comprising a liquid crystal layer,
 wherein the liquid crystal layer comprises a twisted nematic mode.   
     
     
         38 . The display device according to  claim 7 , further comprising a liquid crystal layer,
 wherein the liquid crystal layer comprises a twisted nematic mode.   
     
     
         39 . The display device according to  claim 3 , wherein the oxide semiconductor has a carrier concentration of less than 1×10 14 /cm 3 . 
     
     
         40 . The display device according to  claim 4 , wherein the holding period is variable in accordance with a holding rate of a voltage applied to a display element during the holding period. 
     
     
         41 . The display device according to  claim 5 , wherein a polarity of a voltage applied to a display element is inverted in each of the plurality of frame periods. 
     
     
         42 . The display device according to  claim 2 ,
 wherein the display device is configured to perform display in a plurality of frame periods,   wherein each of the plurality of frame periods includes a writing period and a holding period, and   wherein the holding period is within a range such that an image burn-in does not occur.   
     
     
         43 . The display device according to  claim 3 ,
 wherein the display device is configured to perform display in a plurality of frame periods,   wherein each of the plurality of frame periods includes a writing period and a holding period, and   wherein the holding period is within a range such that an image burn-in does not occur.   
     
     
         44 . The display device according to  claim 7 ,
 wherein the display device is configured to perform display in a plurality of frame periods,   wherein each of the plurality of frame periods includes a writing period and a holding period, and   wherein the holding period is within a range such that an image burn-in does not occur.   
     
     
         45 . The display device according to  claim 3 , further comprising a liquid crystal material adjacent to the pixel electrode,
 wherein a specific resistance of the liquid crystal material measured at 20° C. is 1×10 12  Ω·cm or more.   
     
     
         46 . The display device according to  claim 4 , further comprising a liquid crystal material adjacent to the pixel electrode,
 wherein a specific resistance of the liquid crystal material measured at 20° C. is 1×10 12  Ω·cm or more.   
     
     
         47 . The display device according to  claim 5 , further comprising a liquid crystal material adjacent to the pixel electrode,
 wherein a specific resistance of the liquid crystal material measured at 20° C. is 1×10 12  Ω·cm or more.   
     
     
         48 . The display device according to  claim 6 , further comprising a liquid crystal material adjacent to the pixel electrode,
 wherein a specific resistance of the liquid crystal material measured at 20° C. is 1×10 12  Ω·cm or more.   
     
     
         49 . The display device according to  claim 7 , further comprising a liquid crystal material adjacent to the pixel electrode,
 wherein a specific resistance of the liquid crystal material measured at 20° C. is 1×10 12  Ω·cm or more.   
     
     
         50 . The display device according to  claim 2 , wherein the specific resistance of the liquid crystal material measured at 20° C. is 1×10 14  Ω·cm or more. 
     
     
         51 . The display device according to  claim 4 , wherein a refresh operation is performed at a timing when a voltage applied to a display element is decreased to a predetermined level with respect to an initial value. 
     
     
         52 . The display device according to  claim 5 , wherein the display device is driven by dot inversion driving. 
     
     
         53 . The display device according to  claim 6 , wherein the display device is driven by dot inversion driving. 
     
     
         54 . The display device according to  claim 7 , wherein the display device is driven by dot inversion driving.

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