Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards

Abstract

A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

What is claimed is: 
     
         1 . A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:
 a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and   a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;   wherein at least some of the same megafunctions are used with algorithms of two or more protocols.   
     
     
         2 . The chip architecture according to  claim 1 , wherein at least some of the megafunctions are parameterized, the parameters of at least some of the megafunctions are adapted to be dynamically changed depending on the communication protocol. 
     
     
         3 . The chip architecture according to  claim 2 , further including buses interconnecting the megafunctions, and wherein the size of at least some of the buses are adapted to be dynamically changed depending on the communication protocol. 
     
     
         4 . The chip architecture according to  claim 2 , wherein the control signals for changing parameters of the parameterized megafunctions are stored in memory. 
     
     
         5 . The chip architecture according to  claim 2 , wherein the control signals for changing the parameters of the parameterized megafunctions are inserted on-line from outside the chip architecture. 
     
     
         6 . The chip architecture according to  claim 1 , wherein the control signals are stored in memory. 
     
     
         7 . The chip architecture according to  claim 1 , wherein the control signals are inserted on-line from outside the chip architecture. 
     
     
         8 . The chip architecture according to  claim 1 , further including an interconnect network among the megafunctions, and memory for storing a set of signals for reconfiguring the megafunctions and interconnect network between the megafunctions so as to set the parameters and algorithms associated with the protocol of the signals being processed. 
     
     
         9 . The chip architecture according to  claim 1 , further including an analyzer configured so as to determine the protocol of the signal processed by the chip architecture, and apply the necessary control signals so as to configure the switches and interconnect the necessary megafunctions for processing the signals according to the determined protocols. 
     
     
         10 . The chip architecture according to  claim 9 , wherein the analyzer is an algorithm performed by the system architecture. 
     
     
         11 . The chip architecture according to  claim 10 , wherein the analyzer is an algorithm for checking the strength of the signals processed by the chip architecture. 
     
     
         12 . The chip architecture according to  claim 9 , wherein the analyzer is responsive to the user input to the system architecture. 
     
     
         13 . The chip architecture according to  claim 1 , further including a control for sensing the protocol of the signal, and operating the switches and configuring the megafunctions accordingly. 
     
     
         14 . The chip architecture according to  claim 1 , wherein the protocol for processing of the signal is determined by a hand-off protocol between communication standards. 
     
     
         15 . The chip architecture according to  claim 1 , wherein at least one protocol implements the same algorithm at different stages of the protocol, as a function of a change in the receipt/transmission conditions. 
     
     
         16 . The chip architecture according to  claim 1 , wherein at least one protocol implements the same algorithm at different megafunctions of the same stage of the protocol as a function of a change in the receipt/transmission conditions. 
     
     
         17 . The chip architecture for use in processing signals encoded in accordance with any one of a plurality of protocols each defined by a series of algorithms, comprising:
 a plurality of megafunctions;   a plurality of switches configured to selectively interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; and   memory for storing control signals applied to the switches as a function of the protocol of the signals to be processed.   
     
     
         18 . The chip architecture according to  claim 17 , wherein one or more of the megafunctions is configured to implement algorithms involving orthogonal transforms of said signals. 
     
     
         19 . The chip architecture according to  claim 17 , wherein one or more of the megafunctions is configured to implement algorithms involving cosine and sine transforms. 
     
     
         20 . The chip architecture according to  claim 17 , wherein one or more of the megafunctions is configured to implement algorithms involving Hilbert transforms.