Transistor having hard-mask layers

Abstract

A method for fabricating a transistor including the following steps is provided. First, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the substrate in sequence, wherein the gate insulating layer covers the substrate and the gate electrode. Next, a patterned channel layer and a hard-mask layer are formed on the gate insulating layer, wherein the patterned channel layer and the hard-mask layer are located above the gate electrode, and the hard-mask layer is disposed on the patterned channel layer. Afterwards, a source and a drain are formed on the gate insulating layer by a wet etchant. The part of the hard-mask layer that is not covered by the source and the drain is removed by the wet etchant until the patterned channel layer is exposed, so as to form a plurality of patterned hard-mask layers.

What is claimed is: 
     
         1 . A transistor, comprising:
 a gate electrode;   a gate insulating layer covering the gate electrode;   a patterned channel layer, disposed on the gate insulating layer and is located above the gate electrode;   a plurality of patterned hard-mask layers, disposed on the patterned channel layer, wherein a part of the patterned channel layer is not covered by the patterned hard-mask layers; and   a source and a drain, located on the gate insulating layer, wherein the patterned hard-mask layers are respectively disposed between the source and the patterned channel layer and between the drain and the patterned channel layer, and a material of the patterned hard-mask layers is the same as at least part of a material of the source and the drain.   
     
     
         2 . The transistor according to  claim 1 , wherein the material of the patterned hard-mask layers comprise tin-free oxide semiconductor, and the material of the patterned channel layer comprises tin-containing oxide semiconductor or poly-Indium-Gallium Oxide (poly-IGO). 
     
     
         3 . The transistor according to  claim 1 , wherein the material of the patterned hard-mask layers comprise IGO, IZO, IGZO, AZO, ZnO, In 2 O 3 , or Ga 2 O 3 , and the material of the patterned channel layer comprises ITZO, ZTO, ZTO:In, ZTO:Ga, IGZO:Sn, GTO, IGTO, or poly-Indium-Gallium Oxide (poly-IGO). 
     
     
         4 . The transistor according to  claim 1 , wherein a sheet resistance of the patterned channel layer ranges from 10 7  ohm/unit area to 10 10  ohm/unit area.