Method for Producing a Semiconductor Component with Insulated Semiconductor Mesas in a Semiconductor Body

Abstract

A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

What is claimed is: 
     
         1 . A method for producing a semiconductor component, comprising:
 providing a semiconductor body with a first surface and a second surface opposite to the first surface;   forming an insulation trench from the first surface into the semiconductor body;   forming a first insulation layer at least on one or more sidewalls of the insulation trench;   removing semiconductor material of the semiconductor body from the second surface to expose bottom portions of the first insulation layer and to form a back surface; and,   depositing a second insulation layer on the back surface, such that at least two semiconductor mesas are formed which are insulated from each other by the first insulation layer and the second insulation layer.   
     
     
         2 . The method of  claim 1 , wherein the second insulation layer comprises at least one of silicon oxide, silicone nitride, silicon oxynitride, aluminum nitride, diamond like-carbon, boron-silicate glass, a spin-on glass, a silicone, a polymerized imide, a parylene or a polymerized benzocyclobutene, an organosilicate dielectric, a synthetic material, and a cured resin. 
     
     
         3 . The method of  claim 1 , wherein the insulation trench is completely filled with the first insulation layer. 
     
     
         4 . The method of  claim 1 , further comprising filling the insulation trench with a conductive material prior to depositing the second insulation layer. 
     
     
         5 . The method of  claim 1 , wherein the second insulation layer is mask-less deposited on the back surface. 
     
     
         6 . The method of  claim 1 , wherein forming the insulation trench comprises a Bosch process. 
     
     
         7 . The method of  claim 1 , wherein the insulation trench forms a closed loop. 
     
     
         8 . The method of  claim 1 , wherein removing semiconductor material of the semiconductor body comprises at least one of grinding, polishing, a CMP-process and etching. 
     
     
         9 . The method of  claim 1 , wherein the semiconductor body is thinned to a vertical thickness between the first surface and the back surface of less than about 50 μm by removing semiconductor material of the semiconductor body. 
     
     
         10 . The method of  claim 1 , wherein the semiconductor body comprises an epitaxial layer and wherein the insulation trench is etched completely through the epitaxial layer. 
     
     
         11 . The method of  claim 1 , wherein the semiconductor body is thinned to a vertical thickness between the first surface and the back surface by removing semiconductor material of the semiconductor body, wherein the insulation trench is etched to a vertical depth, and wherein the vertical thickness is about 5% to 30% smaller than the vertical depth. 
     
     
         12 . The method of  claim 1 , further comprising mounting the semiconductor body with the first surface on a carrier system prior to removing semiconductor material of the semiconductor body. 
     
     
         13 . The method of  claim 12 , wherein mounting the semiconductor body on the carrier system comprises attaching the semiconductor body to a glass substrate. 
     
     
         14 . The method of  claim 1 , further comprising at least one of:
 forming a diode structure in at least one of the at least two semiconductor mesas;   forming a capacitance structure in or on at least one of the at least two semiconductor mesas;   forming a transistor structure in at least one of the at least two semiconductor mesas;   forming a gate electrode structure on the first surface and on at least one of the at least two semiconductor mesas;   forming a trench gate electrode structure extending form the first surface into at least one of the at least two semiconductor mesas; and;   forming on the first surface a wiring between the at least two semiconductor mesas and/or to the diode structure and/or to the capacitance structure and/or to the transistor structure and/or to the gate electrode structure and/or to the trench gate electrode structure.   
     
     
         15 . The method of  claim 1 , further comprising at least one of:
 partially removing the second insulation layer to expose at least one of the at least two semiconductor mesas on the back side; and,   forming a metallization on the back side in ohmic contact with the at least one of the at least two semiconductor mesas.   
     
     
         16 . A method for producing a semiconductor component, comprising:
 providing a semiconductor body with a first surface and a second surface opposite to the first surface;   etching an insulation trench from the first surface partially into the semiconductor body;   forming a first insulation layer on one or more sidewalls of the insulation trench;   processing the second surface comprising at least one of grinding, polishing, a CMP-process and etching to expose the first insulation layer; and,   depositing on the processed second surface a second insulation layer which extends to the first insulation layer.   
     
     
         17 . The method of  claim 16 , wherein at least two semiconductor mesas are formed in the semiconductor body which are laterally insulated from each other by the first insulation layer. 
     
     
         18 . The method of  claim 17 , wherein at least one of the two semiconductor mesas is completely insulated on the back surface by the second insulation layer after finishing processing the semiconductor component. 
     
     
         19 . The method of  claim 17 , further comprising prior to processing the second surface at least one of:
 forming an electric component in or on at least one of the at least two semiconductor mesas; and,   forming on the first surface a wiring between the at least two semiconductor mesas and/or to the electric component.   
     
     
         20 . The method of  claim 16 , further comprising finishing processing the semiconductor component from the first surface prior to processing the second surface. 
     
     
         21 . The method of  claim 16 , further comprising prior to processing the second surface forming a TEDFET-structure in the semiconductor body, wherein the first insulation layer forms an accumulation oxide of the TEDFET-structure. 
     
     
         22 . A semiconductor component, comprising:
 a semiconductor body with a first surface and a back surface opposite to the first surface;   at least one insulation trench formed in the semiconductor body and comprising a first insulation layer extending from the first surface to the back surface;   a second insulation layer deposited on the back surface of the semiconductor body, the second insulation layer comprising at least one of aluminum nitride, diamond like-carbon, boron-silicate glass, a spin-on glass, an organosilicate dielectric, a silicone, a polymerized imide, a parylene or a polymerized benzocyclobutene, a synthetic material, and a cured resin; and,   at least two semiconductor mesas formed in the semiconductor body, the at least two semiconductor mesas being laterally insulated from each other by the first insulation layer, and at least one of the two semiconductor mesas being completely insulated on the back surface by the second insulation layer.   
     
     
         23 . The semiconductor component of  claim 22 , wherein the semiconductor component is a TEDFET, and wherein the first insulation layer of the at least one insulation trench forms an accumulation oxide of the TEDFET. 
     
     
         24 . The semiconductor component of  claim 22 , comprising a plurality of semiconductor mesas which are insulated from each other by respective insulation trenches and the second insulation layer. 
     
     
         25 . The semiconductor component of  claim 22 , wherein the at least one insulation trench is substantially void-free.