Replacement gate multigate transistor for embedded dram

Abstract

A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

1 .- 8 . (canceled) 
     
     
         9 . A memory cell comprising:
 a trench capacitor;   a non-planar transistor; and   a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.   
     
     
         10 . The memory cell of  claim 9 , further comprising:
 a shallow trench isolation dielectric formed above the trench capacitor; and   a signal line that passes over the trench capacitor, the signal line being separated from the trench capacitor by the shallow trench isolation dielectric.   
     
     
         11 . The memory cell of  claim 10 , wherein the self-aligned silicide interconnect is formed, at least in part, upon an exposed surface of the trench capacitor revealed by a partially removed section of the shallow trench isolation dielectric. 
     
     
         12 . The memory cell of  claim 9 , wherein the non-planar transistor includes a transistor gate assembly and a transistor channel, the transistor gate assembly having multiple gate surfaces coupled to the transistor channel. 
     
     
         13 . The memory cell of  claim 12 , wherein the non-planar transistor is a fully depleted finFET device. 
     
     
         14 . The memory cell of  claim 12 , wherein the non-planar transistor is a nano-wire multigate device, the transistor gate assembly surrounding the transistor channel on surfaces of the transistor channel parallel to the length of the transistor channel. 
     
     
         15 . A memory array comprising:
 a plurality of DRAM memory cells, the DRAM memory cells each comprising:
 a trench capacitor; 
 a non-planar transistor; and 
 a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor; and 
   a processor, wherein the processor and the plurality of DRAM cells are both formed in a monolithic silicon substrate.   
     
     
         16 . The memory array of  claim 15 , wherein the DRAM memory cells further comprise:
 a shallow trench isolation dielectric formed above the trench capacitor; and   a signal line that passes over the trench capacitor, the signal line being separated from the trench capacitor by the shallow trench isolation dielectric, the signal line configured to carry electrical signals from the plurality of DRAM memory cells.   
     
     
         17 . The memory array of  claim 16 , wherein the self-aligned silicide interconnect is formed, at least in part, upon an exposed surface of the trench capacitor revealed by a partially removed section of the shallow trench isolation dielectric. 
     
     
         18 . The memory array of  claim 15 , wherein the non-planar transistor includes a transistor gate assembly and a transistor channel, the transistor gate assembly having multiple gate surfaces coupled to the transistor channel. 
     
     
         19 . The memory array of  claim 18 , wherein the non-planar transistor is a fully depleted finFET transistor. 
     
     
         20 . The memory array of  claim 18 , wherein the non-planar transistor is a nano-wire multigate device, the transistor gate assembly surrounding surfaces on the transistor channel parallel to the length of the transistor channel.