Instructions and Logic to Provide Memory Access Key Protection Functionality

Abstract

Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.

What is claimed is: 
     
         1 . A processor comprising:
 a control register to store a memory protection field having a first value;   a cache to store cache coherent data in one or more cache lines for one or more memory addresses of a primary storage;   a decode circuit to decode a first instruction specifying a register operand, an addressing form field for a memory operand to specify said one or more memory addresses, and a memory protection key; and   execution circuitry, responsive to a decoded first instruction having an addressing form field having a second value, to:
 enforce memory protection according to said first value of the memory protection field, using the memory protection key, for accessing said one or more memory addresses, and 
 fault when a portion of the memory protection key specified by the decoded first instruction does not match one or more stored key values associated with said one or more memory addresses. 
   
     
     
         2 . The processor of  claim 1 , wherein the fault is a general protection fault. 
     
     
         3 . The processor of  claim 1 , wherein said first value of the memory protection field specifies protected write access. 
     
     
         4 . The processor of  claim 3 , wherein said first value of the memory protection field also specifies protected read access. 
     
     
         5 . The processor of  claim 3 , wherein the register operand is a general purpose scalar register. 
     
     
         6 . The processor of  claim 3 , wherein the register operand is a global descriptor table register. 
     
     
         7 . The processor of  claim 3 , wherein the register operand is a local descriptor table register. 
     
     
         8 . The processor of  claim 3 , wherein the register operand is an interrupt descriptor table register. 
     
     
         9 . The processor of  claim 1 , wherein the addressing form field comprises a scale-index-base (SIB) byte having a value selected from the group consisting of the hexadecimal values: 25, 65, A5 and E5. 
     
     
         10 . The processor of  claim 9 , wherein the addressing form field comprises a ModR/M byte having a value selected from the group consisting of the hexadecimal values: 84, 8C, 94, 9C, A4, AC, B4 and BC. 
     
     
         11 . The processor of  claim 10 , wherein the memory protection key is specified as a 32-bit displacement field. 
     
     
         12 . The processor of  claim 10 , wherein the memory protection key is specified as a value in an index register. 
     
     
         13 . The processor of  claim 9 , wherein the addressing form field comprises a ModR/M byte having a value selected from the group consisting of the hexadecimal values: 44, 4C, 54, 5C, 64, 6C, 74 and 7C. 
     
     
         14 . The processor of  claim 13 , wherein the memory protection key is specified as an 8-bit displacement field.