Adaptive error correction in memory devices

Abstract

Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

1 . An apparatus comprising:
 an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells; and   a control unit to monitor errors in information retrieved from the memory cells and generate control information based on the errors in the information to cause a memory cell among the memory cells to change to from a state among the plurality of states to an additional state, the additional state being different from the plurality of states.   
     
     
         2 . The apparatus of  claim 1 , wherein the additional state is an irreversible state, the irreversible state is an identifiable state when the memory cell is accessed. 
     
     
         3 . The apparatus of  claim 1 , wherein the additional state is not configured to indicate a value of information stored in the memory cell. 
     
     
         4 . The apparatus of  claim 1 , wherein the control unit is configured to provide information to be stored in the memory cell after the memory cell changes from the state among the plurality of states to the additional state, and the memory cell remains in the additional state after the information is stored in the memory cell. 
     
     
         5 . The apparatus of  claim 4 , wherein the control unit is configured to perform an error detection and correction operation to determine a value of information retrieved from the memory cell. 
     
     
         6 . The apparatus of  claim 1 , wherein the memory cell includes a memory element, the memory element has a first resistance when the memory cell is in the first state, a second resistance when the memory cell is in the second state, and a third resistance when the memory cell is in the additional state, and the third resistance has value less than a value of each of the first and second resistances. 
     
     
         7 . The apparatus of  claim 1 , wherein the control unit is configured to generate the control information if a number of occurrences of errors in information retrieved from the memory cell exceeds a value before the memory cell changes from the state among the plurality of states to the additional state. 
     
     
         8 . The apparatus of  claim 1 , wherein the control unit is configured to generate the control information if errors in the information retrieved from the memory cell occur in a number of read operations before the memory cell changes from the state among the plurality of states to the additional state. 
     
     
         9 . The apparatus of  claim 1 , wherein the control unit is configured to adjust a scrub rate associated with the memory cells after the memory cell changes from the state among the plurality of states to the additional state. 
     
     
         10 . The apparatus of  claim 1 , wherein the memory cell and the control unit are included in a cache memory, and the cache memory does not have spare memory cells. 
     
     
         11 . An apparatus comprising:
 an interface to receive information from memory cells, the memory cells comprising a memory cell determined to be defective, the information including a bit stored in the memory cell; and   a control unit to assign at least one value to the bit, to perform at least one error detection and correction operation on the information and to provide data based on the at least one error detection and correction operation.   
     
     
         12 . The apparatus of  claim 11 , wherein the control unit is configured to:
 assign a first value to the bit and perform a first error detection and correction operation;   assign a second value to the bit if the first error detection and correction operation unsuccessfully provides the data, and perform a second error detection and correction operation on the information after assigning the second value to the bit; and   provide the data based on one of the first and second error detection and correction operations.   
     
     
         13 . The apparatus of  claim 12 , wherein the first value comprises binary 0 and the second value comprises binary 1. 
     
     
         14 . The apparatus of  claim 12 , wherein the first value comprises binary 1 and the second value comprises binary 0. 
     
     
         15 . The apparatus of  claim 11 , wherein the control unit is configured to:
 assign a first value to the bit, and perform a first error detection and correction operation on the information;   assign a second value to the bit, and perform a second error detection and correction operation on the information; and   provide the data based on one of the first and second error detection and correction operations.   
     
     
         16 . The apparatus of  claim 11 , wherein the control unit is configured to generate error correction code based on input data to provide information to be stored in the memory cells and in the memory cell determined to be defective. 
     
     
         17 . The apparatus of  claim 11 , wherein the control unit is included in a cache memory controller. 
     
     
         18 . The apparatus of  claim 11 , wherein the memory cells comprise spin-torque transfer random access memory (STT-RAM) memory cells. 
     
     
         19 . An apparatus comprising:
 a first memory cell configured to store information, the first memory cell including a first memory element configured to be changed between a first state and a second state, the first state indicating a first value of information stored in the first memory cell, the second state indicating a second value of information stored in the first memory cell; and   a second memory cell configured to store information, the second memory cell including a second memory element having one of the first state, the second state, and a third state, the third state unable to be changed to either the first state or the second state.   
     
     
         20 . The apparatus of  claim 19 , wherein the first memory element has a first resistance in the first state and a second resistance in the second state. 
     
     
         21 . The apparatus of  claim 20 , wherein the second memory element has a third resistance in the third state, and a value of the third resistance is less than a value of each of the first and second resistances. 
     
     
         22 . The apparatus of  claim 19 , wherein the second memory cell is coupled to a circuit path between a node and ground, and the node is configured to receive a first voltage during a first access to the second memory cell and a second voltage during a second access to the second memory cell, and a value of information stored in the second memory cell is based on a value of a signal on the circuit path during at least one of the first and second accesses. 
     
     
         23 . An apparatus comprising:
 a processing core; and   a cache memory coupled to the processing core, the cache memory comprising:
 memory cells; and 
 a cache controller to monitor errors in information retrieved from the memory cells and generate control information based on the errors in the information to cause an irreversible change in a state of a memory cell among the memory cells. 
   
     
     
         24 . The apparatus of  claim 23 , wherein cache controller is configured to generate error correction code based on input data provided to the cache memory and to store the input data and the error correction code in the memory cells, such that at least a portion of the information is stored in the memory cell. 
     
     
         25 . The apparatus of  claim 24 , wherein the cache controller is configured to decode information retrieved from the memory cells to provide output data such that the output data and the input data have a same value.