Leakage compensation circuit for phase-locked loop (pll) large thin oxide capacitors

Abstract

Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.

What is claimed is: 
     
         1 . A circuit comprising:
 a first capacitor;   a first transistor having a drain coupled to the first capacitor;   an amplifier;   a second capacitor;   a first set of switches selectively coupled between the first capacitor and the second capacitor; and   a second set of switches selectively coupled between an output of the amplifier and a gate of the first transistor.   
     
     
         2 . The circuit of  claim 1 , wherein the first capacitor is a different capacitor type than the second capacitor. 
     
     
         3 . The circuit of  claim 1 , wherein the first capacitor comprises a thin oxide capacitor and wherein the second capacitor comprises a thick oxide capacitor. 
     
     
         4 . The circuit of  claim 1 , further comprising a third capacitor coupled between a source and the gate of the first transistor and configured to maintain a gate-to-source voltage of the first transistor when the second set of switches is open. 
     
     
         5 . The circuit of  claim 1 , further comprising a resistor coupled in series with the first capacitor, wherein:
 the first set of switches is selectively coupled between a first terminal of the resistor and a first terminal of the second capacitor and is selectively coupled between a second terminal of the resistor and a second terminal of the second capacitor; and   the second terminal of the resistor is coupled in series with the first capacitor and is coupled to the drain of the first transistor.   
     
     
         6 . The circuit of  claim 5 , wherein the second set of switches is selectively coupled between the first terminal of the second capacitor and a first input of the amplifier and is selectively coupled between the second terminal of the second capacitor and a second input of the amplifier. 
     
     
         7 . The circuit of  claim 6 , wherein the first set of switches is selectively coupled between inputs of the amplifier and a common-mode voltage node. 
     
     
         8 . The circuit of  claim 7 , wherein the first set of switches is configured to be closed for the circuit to:
 store, across the second capacitor, a leakage voltage based on a leakage current of the first capacitor; and   short the first and second inputs of the amplifier to the common-mode voltage node.   
     
     
         9 . The circuit of  claim 8 , wherein the second set of switches is configured to be closed for the circuit to:
 sense the leakage voltage stored across the second capacitor with the first and second inputs of the amplifier; and   connect the output of the amplifier with the gate of the first transistor.   
     
     
         10 . The circuit of  claim 1 , further comprising
 a second transistor having a gate coupled to the output of the amplifier and to the gate of the first transistor; and   a third capacitor coupled to a first input of the amplifier and to a drain of the second transistor, wherein the second capacitor is coupled to a second input of the amplifier.   
     
     
         11 . The circuit of  claim 10 , wherein the third capacitor has a leakage current proportional to a leakage current of the first capacitor. 
     
     
         12 . The circuit of  claim 10 , wherein the third capacitor is the same capacitor type as the first capacitor. 
     
     
         13 . The circuit of  claim 10 , wherein the first capacitor and the third capacitor comprise thin oxide capacitors. 
     
     
         14 . The circuit of  claim 10 , wherein a capacitance ratio of the first capacitor to the third capacitor is equal to a size ratio of the first transistor to the second transistor. 
     
     
         15 . The circuit of  claim 10 , wherein the second set of switches is selectively coupled between the gate of the first transistor and the gate of the second transistor. 
     
     
         16 . The circuit of  claim 10 , further comprising a buffer having an input coupled to the first capacitor, wherein the first set of switches is selectively coupled between an output of the buffer and the third capacitor and is selectively coupled between the output of the buffer and the second capacitor. 
     
     
         17 . The circuit of  claim 16 , wherein:
 the buffer is configured to buffer a leakage voltage based on a leakage current of the first capacitor; and   the first set of switches is configured to be closed for the circuit to store the buffered leakage voltage across the second capacitor and across the third capacitor.   
     
     
         18 . The circuit of  claim 17 , wherein the second set of switches is configured, when opened, to disconnect the output of the amplifier from the gate of the first transistor and wherein the first set of switches is configured, when opened, to disconnect the output of the buffer from the second capacitor and from the third capacitor. 
     
     
         19 . The circuit of  claim 1 , wherein the first set of switches is configured to be closed for the circuit to sample a leakage voltage based on a leakage current of the first capacitor. 
     
     
         20 . The circuit of  claim 19 , wherein:
 the first transistor is configured to source current for injection into the first capacitor; and   the amplifier is configured to control the first transistor based on the sampled leakage voltage such that the sourced current is approximately equal to the leakage current.   
     
     
         21 . The circuit of  claim 20 , further comprising a resistor coupled in series with the first capacitor, wherein the sourced current is injected into the first capacitor such that a voltage drop across the resistor is approximately zero volts. 
     
     
         22 . A phase-locked loop (PLL) comprising the circuit of  claim 1 , wherein the first capacitor is a filter capacitor in a filter for the PLL. 
     
     
         23 . The circuit of  claim 22 , wherein the PLL further comprises a charge pump, wherein the first set of switches is configured to be closed when the charge pump is inactive and wherein the second set of switches is configured to be closed when the charge pump is active.