Contact-first field-effect transistors

Abstract

Device structures and fabrication methods for a fin-type field-effect transistor. A first contact, a second contact, and a gate electrode are formed on a fin comprised of a semiconductor material. The second contact is spaced along a length of the fin from the first contact. The gate electrode is positioned along the length of the fin between the first contact and the second contact.

1 : A method for forming a device structure, the method comprising:
 forming a fin comprised of a semiconductor material;   forming a first contact on the fin;   forming a second contact on the fin and spaced along a length of the fin from the first contact; and   forming a gate electrode on the fin that is positioned along the length of the fin between the first contact and the second contact.   
     
     
         2 : The method of  claim 1  further comprising:
 forming a first dielectric spacer between the first contact and the gate electrode. 
 
     
     
         3 : The method of  claim 2  further comprising:
 forming a second dielectric spacer between the second contact and the gate electrode. 
 
     
     
         4 : The method of  claim 3  wherein the first dielectric spacer and the second dielectric spacer each include a dopant providing a solid-state diffusion source, and comprising:
 doping a first portion of the fin with the dopant from the first dielectric spacer to define a first source/drain region; and 
 doping a second portion of the fin with the dopant from the second dielectric spacer to define a second source/drain region. 
 
     
     
         5 : The method of claim further comprising:
 removing the first dielectric spacer; and   forming a second dielectric spacer between the first contact and the gate electrode.   
     
     
         6 : The method of  claim 5  wherein the first dielectric spacer is comprised of a first dielectric material having a first relative permittivity, and the first dielectric spacer is comprised of a second dielectric material having a second relative permittivity less than the first relative permittivity. 
     
     
         7 : The method of  claim 1  wherein the first contact and the second contact each include a first layer comprised of a first material and a second layer comprised of a second material. 
     
     
         8 : The method of  claim 7  wherein the first material comprises a dopant providing a solid-state diffusion source, and comprising:
 doping a first portion of the fin with the dopant from the first material of the first contact to define a first source/drain region; and 
 doping a second portion of the fin with the dopant from the first material of the second contact to define a second source/drain region. 
 
     
     
         9 : The method of  claim 1  wherein the first contact has a top surface, and the gate electrode has a top surface that is recessed below the top surface of the gate electrode to define a cavity between the first contact and the second contact. 
     
     
         10 : The method of  claim 9  further comprising:
 forming a dielectric layer in the cavity between the first contact and the second contact. 
 
     
     
         11 : A device structure comprising:
 a fin comprised of a semiconductor material;   a first contact that partially wraps around a first end of the fin;   a second contact that partially wraps around a second end of the fin, the second contact spaced along a length of the fin from the first contact, and the first end of the fin is opposite to the second end of the fin; and   a gate electrode on the fin, the gate electrode formed self-aligned between the first contact and the second contact.   
     
     
         12 : The device structure of  claim 11  further comprising:
 a first spacer between the first contact and the gate electrode, the first spacer comprised of a dielectric material. 
 
     
     
         13 : The device structure of  claim 12  further comprising:
 a second spacer between the second contact and the gate electrode, the second spacer comprised of the dielectric material. 
 
     
     
         14 : The device structure of  claim 13  wherein the first spacer and the second spacer include a dopant providing a solid-state diffusion source for doping the fin. 
     
     
         15 : The device structure of  claim 12  wherein the dielectric material is a low-K dielectric material. 
     
     
         16 : The device structure of  claim 11  wherein the first contact and the second contact each include a first layer comprised of a first material and a second layer comprised of a second material, a channel length of the device structure is established without a positive lithographic process, and the first contact and the second contact cover respective portions of an exterior portion of the fin. 
     
     
         17 : The device structure of  claim 16  wherein the first material of the first layer includes a dopant providing a solid-state diffusion source for doping the fin, and the first contact and the second contact are in direct contact with a top surface of a buried insulator layer of the device structure. 
     
     
         18 : The device structure of  claim 17  wherein the first layer is positioned between the second layer and the fin. 
     
     
         19 : The device structure of  claim 11  wherein the first contact has a top surface, and the gate electrode has a top surface that is recessed below the top surface of the gate electrode to define a cavity between the first contact and the second contact. 
     
     
         20 : The device structure of  claim 19  further comprising:
 a dielectric layer in the cavity between the first contact and the second contact.