Semiconductor packages and methods for fabricating the same

Abstract

A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.

1 . A semiconductor package comprising:
 a first semiconductor chip mounted on a package substrate, the first semiconductor chip comprising:
 a first surface facing the package substrate; 
 a second surface opposite of the first surface; and 
 at least one through-electrode extending from the second surface and penetrating at least a portion the first semiconductor chip; 
   a first molding layer disposed on the package substrate surrounding sides of the first semiconductor chip, the first molding layer exposing the second surface of the first semiconductor chip;   a second semiconductor chip stacked on the second surface of the first semiconductor chip, the second semiconductor chip having an overhang portion extending past a first side of the first semiconductor chip in a first direction, and the second semiconductor chip comprising at least one interconnecting terminal electrically connected to the at least one through-electrode; and   a non-conductive film provided between the first semiconductor chip and the second semiconductor chip,   wherein the non-conductive film comprises a first portion that extends beyond the overhang portion of the second semiconductor chip in the first direction, and   wherein the first portion of the non-conductive film is supported by the first molding layer.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the second semiconductor chip has a width measured in the first direction that is larger than a width of the first semiconductor chip measured in the first direction. 
     
     
         3 . The semiconductor package of  claim 2 , further comprising:
 at least one second interconnecting terminal disposed between the first semiconductor chip and the package substrate and electrically connected to the at least one through-electrode,   wherein the at least one second interconnecting terminal electrically connects the first semiconductor chip to the package substrate.   
     
     
         4 . The semiconductor package of  claim 2 , wherein the at least one interconnecting terminal is disposed in a central region of the second semiconductor chip, and
 wherein the at least one interconnecting terminal is vertically aligned with the at least one through-electrode.   
     
     
         5 . The semiconductor package of  claim 1 , further comprising:
 a second molding layer covering a sidewall of the second semiconductor chip.   
     
     
         6 . The semiconductor package of  claim 1 , further comprising:
 a heat transfer layer provided on the second semiconductor chip; and   a heat radiating layer provided on the heat transfer layer.   
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 a heat transfer layer surrounding the second semiconductor chip; and   a heat radiating layer provided on the heat transfer layer.   
     
     
         8 . The semiconductor package of  claim 1 , further comprising:
 a third semiconductor chip stacked on the second semiconductor chip,   wherein the second semiconductor chip comprises: a first surface facing the first semiconductor chip, a second surface opposite thereto, and at least one second through-electrode extending from the second surface and at least partially penetrating the second semiconductor chip, and   wherein the third semiconductor chip includes at least one second interconnecting terminal that is electrically connected to the at least one second through-electrode.   
     
     
         9 . A semiconductor package comprising:
 a first semiconductor chip having a first front surface and a first back surface, the first semiconductor chip mounted on a package substrate in such a way that the first front surface faces the package substrate;   a second semiconductor chip having a second front surface and a second back surface, the second semiconductor chip stacked on the first semiconductor chip in such a way that the second front surface faces the first back surface;   a first molding layer provided on the package substrate to mold the first semiconductor chip, the first molding layer exposing the first back surface; and   a non-conductive film provided between the first back surface and the second front surface and supported by the first back surface,   wherein a size of the second semiconductor chip is greater than that of the first semiconductor chip such that the second semiconductor chip has an overhang protruding past a side of the first semiconductor chip,   wherein the first molding layer has an upper surface substantially coplanar with the first back surface, and   wherein the non-conductive film extends past edges of the second front surface such that the non-conductive film has an extending portion that extends onto the surface of the first molding layer at a location that is not under the second semiconductor chip.   
     
     
         10 . The semiconductor package of  claim 9 , wherein the first semiconductor chip comprises through-electrodes that extend from the first back surface and at least partially penetrate the first semiconductor chip so as to be electrically connected to the package substrate, and
 wherein the second semiconductor chip comprises interconnecting terminals that are disposed on the second front surface so as to be electrically connected to the through-electrodes.   
     
     
         11 . The semiconductor package of  claim 10 , wherein the through-electrodes are provided in a central region of the first semiconductor chip,
 wherein the interconnecting terminals are provided in a central region of the second semiconductor chip, and   wherein the interconnecting terminals are vertically aligned with the through-electrodes.   
     
     
         12 . The semiconductor package of  claim 10 , wherein the non-conductive film fills a space between the first back surface and the second front surface, and
 wherein the interconnecting terminals penetrate the non-conductive film so as to be connected to the through-electrodes.   
     
     
         13 . The semiconductor package of  claim 9 , wherein the first molding layer fills a space between the package substrate and the first front surface and extends along sidewalls of the first semiconductor chip to surround the first semiconductor chip. 
     
     
         14 . The semiconductor package of  claim 9 , further comprising:
 a second molding layer extending along sidewalls of the second semiconductor chip to surround the second semiconductor chip, the second molding layer not being formed on the second back surface of the second semiconductor chip.   
     
     
         15 . The semiconductor package of  claim 9 , wherein the first front surface and the second front surface are active surfaces, and
 wherein the first back surface and the second back surface are non-active surfaces.   
     
     
         16 . The semiconductor package of  claim 9 , further comprising:
 a third semiconductor chip having a third front surface and a third back surface, the third semiconductor chip stacked on the second semiconductor chip in such a way that the third front surface faces the second back surface; and   a second non-conductive film provided between the third front surface and the second back surface and supported by the second back surface,   wherein the second semiconductor chip comprises second through-electrodes extending from the second back surface and at least partially penetrating the second semiconductor chip, and   wherein the third semiconductor chip comprises interconnecting terminals that are provided on the third front surface so as to be electrically connected to the second through-electrodes.   
     
     
         17 . A semiconductor package comprising:
 a non-memory chip comprising: a first active surface; a first non-active surface opposite to the first active surface; and through-electrodes extending from the first non-active surface and at least partially penetrating the non-memory chip, the non-memory chip being mounted on a printed circuit board in such a way that the first active surface faces the printed circuit board;   a memory chip comprising: a second active surface having interconnecting terminals electrically connected to the through-electrodes; and a second non-active surface opposite to the second active surface, the memory chip mounted on the non-memory chip in such a way that the second active surface faces the first non-active surface;   a first molding layer provided on the printed circuit board to mold the non-memory chip, the first molding layer having a surface substantially coplanar with the first non-active surface; and   a non-conductive film provided between the non-memory chip and the memory chip and supported by the first non-active surface, a size of the non-conductive film greater than that of the second active surface as measured in a first direction,   wherein the memory chip has an overhang extending over a sidewall of the non-memory chip in the first direction,   wherein the non-conductive film has an extended portion protruding beyond the overhang in the first direction so that the extended portion is not under the memory chip, and   wherein the extended portion of the non-conductive film is supported by the surface of the first molding layer.   
     
     
         18 . The semiconductor package of  claim 17 , wherein the non-memory chip comprises an application processor (AP). 
     
     
         19 . The semiconductor package of  claim 17 , further comprising:
 a second molding layer extending along sidewalls of the memory chip and not covering the second non-active surface.   
     
     
         20 . The semiconductor package of  claim 19 , further comprising:
 a heat transfer layer and a heat radiating layer sequentially stacked on the second non-active surface.   
     
     
         21 - 48 . (canceled)