Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing a semiconductor package are disclosed. The semiconductor package including a first substrate including a first cavity, a cavity mold configured to be inserted into the first cavity and including a second cavity, an electronic component inserted in the second cavity, and a second substrate formed on a surface of the first substrate, a surface of the cavity mold and a surface of the electronic component.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a first substrate comprising a first cavity;   a cavity mold configured to be inserted into the first cavity and comprising a second cavity;   an electronic component inserted in the second cavity; and   a second substrate formed on a surface of the first substrate, a surface of the cavity mold and a surface of the electronic component.   
     
     
         2 . The semiconductor package as set forth in  claim 1 , wherein a plurality of electronic components are disposed above the second substrate. 
     
     
         3 . The semiconductor package as set forth in  claim 2 , wherein the cavity mold comprises a plurality of first cavities configured to receive the plurality of electronic components. 
     
     
         4 . The semiconductor package as set forth in  claim 1 , wherein the cavity mold is made of an insulating material. 
     
     
         5 . The semiconductor package as set forth in  claim 4 , wherein the cavity mold is made of a prepreg. 
     
     
         6 . The semiconductor package as set forth in  claim 1 , wherein the cavity mold is made at least one of a prepreg, a metal, or a ceramic. 
     
     
         7 . The semiconductor package as set forth in  claim 1 , wherein another surface of the cavity mold and another surface of the electronic component are placed on a same plane. 
     
     
         8 . The semiconductor package as set forth in  claim 1 , wherein the second substrate comprises an insulating layer and a circuit layer, and the insulating layer is made of a photosensitive insulating material. 
     
     
         9 . The semiconductor package as set forth in  claim 1 , wherein the first substrate comprises an insulating layer and a circuit layer. 
     
     
         10 . The semiconductor package as set forth in  claim 9 , wherein the cavity mold is configured to prevent the insulating layer from flowing into the electronic component. 
     
     
         11 . The semiconductor package as set forth in  claim 1 , wherein a surface of the cavity mold in which the electronic component is inserted is flat. 
     
     
         12 . A method of manufacturing a semiconductor package, comprising:
 preparing a first substrate comprising a first cavity formed;   preparing a cavity mold comprising a second cavity;   inserting an electronic component in the second cavity;   inserting the cavity mold in the first cavity; and   forming a second substrate on a surface of the first substrate, a surface of the cavity mold, and a surface of the electronic component.   
     
     
         13 . The method as set forth in  claim 12 , wherein the cavity mold is made of an insulating material. 
     
     
         14 . The method as set forth in  claim 13 , wherein the cavity mold is made of a prepreg. 
     
     
         15 . The method as set forth in  claim 12 , wherein the cavity mold is made of a metal or a ceramic. 
     
     
         16 . The method as set forth in  claim 12 , wherein the second cavity comprises a plurality of cavities formed thereon. 
     
     
         17 . The method as set forth in  claim 16 , wherein the inserting of the electronic component comprises inserting a plurality of electronic components in the plurality of second cavities. 
     
     
         18 . The method as set forth in  claim 13 , wherein another surface of the cavity mold and another surface of the electronic component are placed on a same plane. 
     
     
         19 . The method as set forth in  claim 13 , wherein the second substrate comprises an insulating layer and a circuit layer, and the insulating layer is made of a photosensitive insulating material.