Chip packages with reduced temperature variation

Abstract

Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

What is claimed is: 
     
         1 . A chip package comprising:
 a device structure including a first emitter finger and a second emitter finger, the first emitter finger and the second emitter finger having at least one parameter; and   a thermal pathway structure configured to influence transport of heat energy emitted from the first emitter finger and the second emitter finger,   wherein the at least one parameter for the first emitter finger and the second emitter finger is selected based upon a first proximity to the thermal pathway structure.   
     
     
         2 . The chip package of  claim 1  wherein the at least one parameter for the first emitter finger and the second emitter finger includes a first width for the first emitter finger and a second width for the second emitter finger, and the first width and the second width are selected based upon the first proximity to the thermal pathway structure. 
     
     
         3 . The chip package of  claim 2  wherein the thermal pathway structure is a heat sink, the first emitter finger is closer to the heat sink than the second emitter finger, and the first width of the first emitter finger is greater than the second width of the second emitter finger. 
     
     
         4 . The chip package of  claim 3  wherein the device structure includes a third emitter finger having a third width, the second emitter finger is located between the first emitter finger and the third emitter finger, the first emitter finger is separated by a first spacing from the second emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is less than the second spacing. 
     
     
         5 . The chip package of  claim 2  wherein the thermal pathway structure is a thermally-insulating package element, the first emitter finger is closer to the thermally-insulating package element than the second emitter finger, and the first width of the first emitter finger is less than the second width of the second emitter finger. 
     
     
         6 . The chip package of  claim 5  wherein the device structure includes a third emitter finger having a third width, the second emitter finger is located between the first emitter finger and the third emitter finger, the first emitter finger is separated by a first spacing from the second emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is greater than the second spacing. 
     
     
         7 . The chip package of  claim 1  wherein the at least one parameter for the first emitter finger and the second emitter finger includes a first spacing between the first emitter finger and the second emitter finger, and the first spacing is selected based upon the first proximity to the thermal pathway structure. 
     
     
         8 . The chip package of  claim 7  wherein the thermal pathway structure is a heat sink, the device structure includes a third emitter finger, the second emitter finger is located between the first emitter finger and the third emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is less than the second spacing. 
     
     
         9 . The chip package of  claim 7  wherein the thermal pathway structure is a thermally-insulating package element, the device structure includes a third emitter finger, the second emitter finger is located between the first emitter finger and the third emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is greater than the second spacing. 
     
     
         10 . The chip package of  claim 1  wherein the first emitter finger and the second emitter finger are located in a first cell, and the device structure further includes a third emitter finger and a fourth emitter finger located in a second cell, the first, second, third, and fourth emitter fingers are connected in parallel at one or more back-end-of-line wiring levels, and the third emitter finger and the fourth emitter finger have at least one parameter based upon a second proximity to the thermal pathway structure that is different from the at least one parameter for the first emitter finger and the second emitter finger. 
     
     
         11 . A method for forming a chip package, the method comprising:
 forming a chip including a device structure with a first emitter finger and a second emitter finger, the first emitter finger and the second emitter finger having at least one parameter; and   forming a thermal pathway structure configured to influence transport of heat energy emitted from the first emitter finger and the second emitter finger,   wherein the at least one parameter for the first emitter finger and the second emitter finger is selected based upon a first proximity to the thermal pathway structure.   
     
     
         12 . The method of  claim 11  wherein the at least one parameter for the first emitter finger and the second emitter finger includes a first width for the first emitter finger and a second width for the second emitter finger, and the first width and the second width are selected based upon the first proximity to the thermal pathway structure. 
     
     
         13 . The method of  claim 12  wherein the thermal pathway structure is a heat sink, the first emitter finger is closer to the heat sink than the second emitter finger, and the first width of the first emitter finger is greater than the second width of the second emitter finger. 
     
     
         14 . The method of  claim 13  wherein the device structure includes a third emitter finger having a third width, the second emitter finger is located between the first emitter finger and the third emitter finger, the first emitter finger is separated by a first spacing from the second emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is less than the second spacing. 
     
     
         15 . The method of  claim 12  wherein the thermal pathway structure is a thermally-insulating package element, the first emitter finger is closer to the thermally-insulating package element than the second emitter finger, and the first width of the first emitter finger is less than the second width of the second emitter finger. 
     
     
         16 . The method of  claim 15  wherein the device structure includes a third emitter finger having a third width, the second emitter finger is located between the first emitter finger and the third emitter finger, the first emitter finger is separated by a first spacing from the second emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is greater than the second spacing. 
     
     
         17 . The method of  claim 11  wherein the at least one parameter for the first emitter finger and the second emitter finger includes a first spacing between the first emitter finger and the second emitter finger, and the first spacing is selected based upon the first proximity to the thermal pathway structure. 
     
     
         18 . The method of  claim 17  wherein the thermal pathway structure is a heat sink, the device structure includes a third emitter finger, the second emitter finger is located between the first emitter finger and the third emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is less than the second spacing. 
     
     
         19 . The method of  claim 17  wherein the thermal pathway structure is a thermally-insulating package element, the device structure includes a third emitter finger, the second emitter finger is located between the first emitter finger and the third emitter finger, the second emitter finger is separated by a second spacing from the third emitter finger, and the first spacing is greater than the second spacing. 
     
     
         20 . The method of  claim 11  wherein the first emitter finger and the second emitter finger are located in a first cell, and the device structure further includes a third emitter finger and a fourth emitter finger located in a second cell, the first, second, third, and fourth emitter fingers are connected in parallel at one or more back-end-of-line wiring levels, and the third emitter finger and the fourth emitter finger have at least one parameter based upon a second proximity to the thermal pathway structure that is different from the at least one parameter for the first emitter finger and the second emitter finger.