Semiconductor structure with junction leakage reduction

Abstract

A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench isolation (STI) and at least one deep trench isolation (DTI). The first well region of a first conductive type is on the semiconductor substrate. The second well region of a second conductive type is on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type. The active region is on the first well region. The active region has a conductive type the same as the second conductive type of the second well region. The STI is between the first and second well regions. The DTI is below the STI. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure, comprising:
 providing a semiconductor substrate;   forming a shallow trench by etching the semiconductor substrate;   forming a protective layer covering the shallow trench;   performing a first etching process to the protective layer until at least a portion of a bottom surface of the shallow trench is exposed by the protective layer;   performing a second etching process on the portion of the bottom surface of the shallow trench, thereby forming at least one deep trench below the bottom surface of the shallow trench;   removing the protective layer remained on the semiconductor substrate and in the shallow trench;   filling an isolation oxide into the deep trench and the shallow trench to form at least one deep trench isolation (DTI) and a shallow trench isolation (STI) respectively;   forming a first well region of a first conductive type on the semiconductor substrate;   forming an active region on the first well region; and   forming a second well region of a second conductive type on the semiconductor substrate and adjacent to the first well region, wherein the second conductive type is different from the first conductive type, and second conductive type is the same a conductive type of the active region;   wherein the first well region and the second well region are formed such that the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.   
     
     
         2 . The method of  claim 1 , wherein the deep trench is formed being located at a corner region of the bottom surface of the shallow trench. 
     
     
         3 . The method of  claim 1 , wherein the first well region is formed such that the DTI has at least a portion located in the first well region. 
     
     
         4 . The method of  claim 1 , wherein the first well region and the second well region are formed such that the DTI has at least a portion located at a boundary between the first well region and the second well region. 
     
     
         5 . The method of  claim 1 , wherein the deep trench is formed having a depth substantially greater than about 1000 angstroms. 
     
     
         6 . The method of  claim 1 , wherein the first etching process comprises a dry etching process, and the second etching process comprises a wet etching process. 
     
     
         7 . The method of  claim 1 , wherein the first well region is formed being a N-type well region, and the second well region is formed being a P-type well region. 
     
     
         8 . The method of  claim 1 , wherein the first well region is formed as a P-type well region, and the second well region is formed as a N-type well region. 
     
     
         9 . The method of  claim 1 , wherein the semiconductor substrate is a P-type semiconductor substrate. 
     
     
         10 . A semiconductor structure, comprising:
 a semiconductor substrate;   a first well region of a first conductive type on the semiconductor substrate;   a second well region of a second conductive type on the semiconductor substrate and adjacent to the first well region, the second conductive type being different from the first conductive type;   an active region on the first well region, wherein a conductive type of the active region is the same as the second conductive type of the second well region;   a shallow trench isolation (STI) between the first well region and the second well region; and   at least one deep trench isolation (DTI) below the STI in the semiconductor substrate, wherein the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the DTI is located at a corner region of a bottom surface of the STI. 
     
     
         12 . The semiconductor structure of  claim 10 , wherein at least a portion of the DTI is located in the first well region. 
     
     
         13 . The semiconductor structure of  claim 10 , wherein at least a portion of the DTI is located at a boundary between the first well region and the second well region. 
     
     
         14 . The semiconductor structure of  claim 10 , wherein a depth of the DTI is substantially greater than about 1000 angstroms. 
     
     
         15 . The semiconductor structure of  claim 10 , wherein the first well region is a N-type well region, and the second well region is a P-type well region. 
     
     
         16 . The semiconductor structure of  claim 10 , wherein the first well region is a P-type well region, and the second well region is a N-type well region. 
     
     
         17 . The semiconductor structure of  claim 10 , wherein the semiconductor substrate is a P-type semiconductor substrate. 
     
     
         18 . A semiconductor structure, comprising:
 a semiconductor substrate;   a first implant region of a first conductive type on the semiconductor substrate;   a second implant region of a second conductive type on the semiconductor substrate, the second conductive type being different from the first conductive type;   a first source/drain electrode in the first implant region;   a second source/drain electrode in the second implant region;   a gate electrode on the semiconductor substrate and between the first source/drain electrode and the second source/drain electrode;   a shallow trench isolation (STI) between the first source/drain electrode and the second source/drain electrode; and   at least one deep trench isolation (DTI) below the STI in the semiconductor substrate, wherein the DTI is disposed between at least a portion of the first implant region and at least a portion of the second implant region.   
     
     
         19 . The semiconductor structure of  claim 18 , wherein the DTI is located at a corner region of a bottom surface of the STI. 
     
     
         20 . The semiconductor structure of  claim 18 , wherein a depth of the DTI is substantially greater than about 1000 angstroms.