Capacitor With 3D NAND Memory

Abstract

An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

1 . An integrated circuit comprising:
 a substrate;   a 3D NAND memory array with a stack of conductive strips; and   a capacitor with a stack of capacitor terminal strips,   wherein multiple conductive strips in the stack of conductive strips and multiple capacitor terminal strips of the stack of capacitor terminal strips share a same plurality of plane positions relative to the substrate, different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the stack of conductive strips is at least one of: transistor channels in the 3D NAND memory array, conductors routing signals that select memory cells in the 3D NAND memory array, and conductors routing output from the 3D NAND memory array. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the 3D NAND memory array is a vertical gate memory array, and the conductive strips in the stack are NAND transistor channels in the vertical gate memory array. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the 3D NAND memory array is a vertical channel memory array, and the conductive strips in the stack are word lines in the vertical channel memory array. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the stack of capacitor terminal strips includes a first plurality of capacitor terminal strips alternating with a second plurality of capacitor terminal strips, the first plurality of capacitor terminal strips electrically connected together and the second plurality of capacitor terminal strips electrically connected together. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the stack of capacitor terminal strips has a first end and a second end, multiple capacitor terminal strips in the stack of capacitor terminal strips electrically connected together at the first end, multiple capacitor terminal strips in the stack of capacitor terminal strips electrically connected together at the second end, further comprising:
 a conductive plug electrically connected to at least one of the capacitor terminal strips at an intermediate point in between the first end and the second end.   
     
     
         7 . The integrated circuit of  claim 1 , wherein the stack of capacitor terminal strips is one of a plurality of stacks of capacitor terminal strips having lengths between first ends and second ends, the plurality of stacks of capacitor terminal strips including the first plurality of capacitor terminal strips alternating with the second plurality of capacitor terminal strips, the first plurality of capacitor terminal strips in the plurality of stacks of capacitor terminal strips electrically connected together via the first ends and at intermediate points in between the first ends and second ends. 
     
     
         8 - 14 . (canceled) 
     
     
         15 . A method of making an integrated circuit, comprising:
 making a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips, including:   in a same etch, defining the stack of conductive strips and the stack of capacitor terminal strips,
 wherein multiple conductive strips in the stack of conductive strips and multiple capacitor terminal strips of the stack of capacitor terminal strips share a same plurality of plane positions relative to the substrate, different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other. a 3D NAND memory array with a stack of conductive strips. 
   
     
     
         16 . The method of  claim 15 , wherein the stack of conductive strips is at least one of:
 transistor channels in the 3D NAND memory array, conductors routing signals that select memory cells in the 3D NAND memory array, and conductors routing output from the 3D NAND memory array.   
     
     
         17 . The method of  claim 15 , wherein the 3D NAND memory array is a vertical gate memory array, and the conductive strips in the stack are NAND transistor channels in the vertical gate memory array. 
     
     
         18 . The method of  claim 15 , wherein the 3D NAND memory array is a vertical channel memory array, and the conductive strips in the stack are word lines in the vertical channel memory array. 
     
     
         19 . The method of  claim 15 , wherein the stack of capacitor terminal strips includes a first plurality of capacitor terminal strips alternating with a second plurality of capacitor terminal strips, the first plurality of capacitor terminal strips electrically connected together and the second plurality of capacitor terminal strips electrically connected together. 
     
     
         20 . The method of  claim 15 , wherein the stack of capacitor terminal strips has a first end and a second end, multiple capacitor terminal strips in the stack of capacitor terminal strips electrically connected together at the first end, multiple capacitor terminal strips in the stack of capacitor terminal strips electrically connected together at the second end, further comprising:
 a conductive plug electrically connected to at least one of the capacitor terminal strips at an intermediate point in between the first end and the second end.   
     
     
         21 . The method of  claim 15 , wherein the stack of capacitor terminal strips is one of a plurality of stacks of capacitor terminal strips having lengths between first ends and second ends, the plurality of stacks of capacitor terminal strips including the first plurality of capacitor terminal strips alternating with the second plurality of capacitor terminal strips, the first plurality of capacitor terminal strips in the plurality of stacks of capacitor terminal strips electrically connected together via the first ends and at intermediate points in between the first ends and second ends.