Package-on-package assembly and method for manufacturing the same

Abstract

A package-on-package assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side; at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; at least one TSV chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the TSV chip comprises at least one TSV connecter and is mounted on the first side through a plurality of second bumps arranged within the peripheral area; a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and a plurality of solder bumps mounted on the second side.

1 . A package-on-package (PoP) assembly, comprising:
 a bottom die package comprising
 a TSV-less interposer having a first side and a second side opposite to the first side; 
 at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps; 
 at least one through-substrate-via (TSV) chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the TSV chip comprises at least one TSV connecter and is mounted on the first side through a plurality of second bumps arranged within the peripheral area; 
 a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip, wherein a top surface of the at least one active chip is flush with a top surface of the molding compound; and 
 a plurality of solder bumps mounted on the second side; 
   a top die package mounted on the bottom die package, wherein the top die package is electrically connected to the bottom die package only through the TSV chip within the peripheral area.   
     
     
         2 . The PoP assembly according to  claim 1 , wherein the TSV-less interposer comprises a redistribution layer (RDL). 
     
     
         3 . The PoP assembly according to  claim 2 , wherein the RDL comprises at least one dielectric layer and at least one metal layer. 
     
     
         4 . The PoP assembly according to  claim 1 , wherein the top die package comprises at least a molded semiconductor die. 
     
     
         5 . The PoP assembly according to  claim 1 , wherein the top die package is mounted on the bottom die package through a plurality of third bumps disposed on the TSV chip. 
     
     
         6 - 9 . (canceled)