Local thinning of semiconductor fins

Abstract

After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor fin located on a substrate, said semiconductor fin having a same semiconductor composition throughout and including a body region, a fin source region, and a fin drain region, wherein a top surface of said body region is recessed relative to top surfaces of said fin source region and said fin drain region; and   a gate stack straddling said body region, wherein sidewalls of a gate dielectric within said gate stack contact sidewalls of said fin source region and said fin drain region.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising another semiconductor fin located on said substrate, wherein a top surface of another body region that is present within said another semiconductor fin is coplanar with top surfaces of another fin source region and another fin drain region that are present within said another semiconductor fin. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein said top surface of said another body region is within a same horizontal plane as said top surfaces of said fin source region and said fin drain region of said semiconductor fin. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein gate stack straddles said another semiconductor fin. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprising a gate spacer including inner sidewalls that vertically coincide with said sidewalls of said gate dielectric. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein said fin source region and said fin drain region have a greater width than an upper portion of said body region. 
     
     
         7 . A semiconductor structure comprising a semiconductor fin located on a substrate and including a first sidewall and a second sidewall, wherein said first and second sidewalls extend along a lengthwise direction of said semiconductor fin, a planar upper portion of said first sidewall is contained within a first planar vertical plane, a planar upper portion of said second sidewall is contained within a second planar vertical plane that is parallel to said first planar vertical plane, and a portion of said first sidewall includes a curved surface that protrudes outward from said first vertical plane by a distance that is greater than a maximum of any lateral deviation of said second sidewall from said second planar vertical plane. 
     
     
         8 . The semiconductor structure of  claim 7 , further comprising another semiconductor fin located on said substrate and including a pair of sidewalls that extend along a lengthwise direction of said another semiconductor fin, wherein said pair of sidewalls include planar portions having a uniform width, and a maximum lateral deviation of each of said pair of sidewalls is the same as said maximum of any lateral deviations of said second sidewall. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein said curved surface is a concave surface having a same curvature along said lengthwise direction of said semiconductor fin. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein said second sidewall includes another concave surface having a lesser radius of curvature than said concave surface. 
     
     
         11 . The semiconductor structure of  claim 7 , wherein said substrate is a bulk semiconductor substrate, said first and second sidewalls are contiguously adjoined to said bulk semiconductor substrate, and a bottommost portion of said first sidewall is vertically coincident with a most distal portion of said curved surface. 
     
     
         12 . The semiconductor structure of  claim 7 , further comprising a gate stack straddling said semiconductor fin.