Integrated Circuit On Corrugated Substrate

Abstract

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

1 . A method of producing an SOI wafer comprising at least the steps of forming on a base wafer an insulator layer and at least a first plurality of parallel ridges having a uniform height, width and spacing formed on the insulator layer. 
     
     
         2 . The method of producing the SOI wafer in  claim 1  further comprising forming a second plurality of parallel ridges having a uniform height, width and spacing, the first and second plurality of parallel ridges each having a selected orientation. 
     
     
         3 . The method of producing the SOI wafer in  claim 2  wherein the first plurality of parallel ridges is perpendicular to the second plurality of parallel ridges. 
     
     
         4 . The method of producing the SOI wafer in  claim 2  wherein the first plurality of parallel ridges is parallel with the second plurality of parallel ridges. 
     
     
         5 . The method of producing an SOI wafer in  claim 1  wherein forming the first plurality of parallel ridges comprise forming the first plurality of parallel ridges from a semiconductor material. 
     
     
         6 . The method of producing an SOI wafer in  claim 1  wherein forming the first plurality of parallel ridges comprise forming the first plurality of parallel ridges from a compound semiconductor material. 
     
     
         7 . The method of producing an SOI wafer in clam  1  wherein forming the first plurality of parallel ridges comprise forming the first plurality of parallel ridges from carbon nanotubes. 
     
     
         8 . The method of producing an SOI wafer in  claim 2  wherein forming the first and second plurality of parallel ridges comprise forming at least one of the first or second plurality of parallel ridges from a semiconductor material. 
     
     
         9 . The method of producing an SOI wafer in  claim 2  wherein forming the first and second plurality of parallel ridges comprise forming at least one of the first or second plurality of parallel ridges from a compound semiconductor material. 
     
     
         10 . The method of producing an SOI wafer in  claim 2  wherein forming the first and second plurality of parallel ridges comprise forming at least the first or second plurality of parallel ridges from carbon nanotubes. 
     
     
         11 . The method of producing the SOI wafer in  claim 2  further comprising forming a ridge isolation material around each of the plurality of semiconductor ridges. 
     
     
         12 . The method of producing the SOI wafer in  claim 2  further comprising forming each of the first and second plurality of ridges with a high precision ridge manufacturing technique controllable to form sub-wavelength features. 
     
     
         13 . The method of producing the SOI wafer in  claim 2  further comprising forming each of the first and second plurality of ridges on a layer of silicon germanium. 
     
     
         14 . The method of producing an SOI wafer in claim.  2  wherein forming the first and second plurality of parallel ridges comprise forming ridges wherein each ridge has a selected width that is less than a critical dimension. 
     
     
         15 . The method of  claim 14  wherein the selected width is less than 20 nanometers. 
     
     
         16 . The method of producing an SOI wafer in  claim 2  wherein forming the first and second plurality of parallel ridges further comprise forming a planar semiconductor surface region. 
     
     
         17 . The method of producing an SOI wafer in  claim 2  wherein forming the first and second plurality of parallel ridges further comprise forming the first and second plurality of parallel ridges such that each covers an area at least as large as required to implement a basic functional block sufficient to perform a selected logic function. 
     
     
         18 . The method of producing an SOI wafer in  claim 2  wherein forming the first and second plurality of parallel ridges further comprise separating the first plurality of parallel ridges from the second set of parallel ridges by a scribe line. 
     
     
         19 . The method of producing an SOI wafer in  claim 1  wherein forming the first plurality of parallel ridges comprises forming ridges wherein each ridge has a selected width that is less than 20 nanometers.