Apparatus having processing pipeline with first and second execution circuitry, and method

Abstract

A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

1 . An apparatus comprising:
 a processing pipeline comprising:   first and second execution circuitry to execute instructions, wherein the first and second execution circuitry have different performance or energy consumption characteristics; and   instruction supply circuitry to supply instructions to the first and second execution circuitry, wherein the instruction supply circuitry supports first and second instruction supply schemes with different performance or energy consumption characteristics.   
     
     
         2 . The apparatus according to  claim 1 , wherein when supplying instructions according to the first instruction supply scheme, the instruction supply circuitry is configured to supply instructions to at least one of the first and second execution circuitry with greater maximum throughput of instructions than when supplying instructions according to the second instruction supply scheme. 
     
     
         3 . The apparatus according to  claim 1 , wherein when supplying instructions according to the second instruction supply scheme, the instruction supply circuitry is configured to consume less energy than when supplying instructions according to the first instruction supply scheme. 
     
     
         4 . The apparatus according to  claim 1 , wherein the instruction supply circuitry comprises fetch circuitry to fetch instructions from an instruction store; and
 the fetch circuitry supports first and second fetch schemes with different performance or energy consumption characteristics.   
     
     
         5 . The apparatus according to  claim 4 , wherein when fetching instructions according to the first fetch scheme, the fetch circuitry is configured to fetch a wider block of instructions per cycle than when fetching instructions according to the second fetch scheme. 
     
     
         6 . The apparatus according to  claim 1 , comprising predecode circuitry to predecode instructions prior to the instructions being stored in an instruction store;
 wherein the predecode circuitry supports first and second predecoding schemes with different performance or energy consumption characteristics.   
     
     
         7 . The apparatus according to  claim 6 , wherein in the first predecoding scheme, the predecode circuitry is configured to generate different information for a predecoded instruction than in the second predecoding scheme. 
     
     
         8 . The apparatus according to  claim 1 , wherein the instruction supply circuitry comprises decode circuitry to decode instructions to be executed by the first and second execution circuitry;
 wherein the decode circuitry supports first and second decode schemes with different performance or energy consumption characteristics.   
     
     
         9 . The apparatus according to  claim 8 , wherein in the first decode scheme, the decode circuitry is configured to decode a greater number of instructions per cycle than in the second decode scheme. 
     
     
         10 . The apparatus according to  claim 1 , wherein the instruction supply circuitry comprises branch prediction circuitry to predict an outcome of branch instructions; and
 the branch prediction circuitry supports first and second branch prediction schemes with different performance or energy consumption characteristics.   
     
     
         11 . The apparatus according to  claim 10 , wherein in the first branch prediction scheme, the branch prediction circuitry is configured to initiate a branch prediction at an earlier stage of the processing pipeline than in the second branch prediction scheme. 
     
     
         12 . The apparatus according to  claim 10 , wherein in the first branch prediction scheme, the branch prediction circuitry is configured to initiate a branch prediction for a selected instruction before the selected instruction is identified as a branch instruction; and
 in the second branch prediction scheme, the branch prediction circuitry is configured to initiate the branch prediction for a selected instruction after the selected instruction has been identified as a branch instruction.   
     
     
         13 . The apparatus according to  claim 10 , wherein in the first branch prediction scheme, the branch prediction circuitry is configured to generate a branch prediction based on a first set of prediction data, and
 in the second branch prediction scheme, the branch prediction circuitry is configured to generate a branch prediction based on a second set of prediction data.   
     
     
         14 . The apparatus according to  claim 13 , wherein the first set of prediction data comprises a greater amount of prediction data than the second set of prediction data. 
     
     
         15 . The apparatus according to  claim 10 , wherein while using the second branch prediction scheme, the branch prediction circuitry is configured to update prediction data used by the first branch prediction scheme in response to outcomes of resolved branch instructions. 
     
     
         16 . The apparatus according to  claim 1 , comprising control circuitry configured to select, for a given set of instructions, whether the instruction supply circuitry is to supply the set of instructions to the first execution circuitry or the second execution circuitry, and whether the instruction supply circuitry is to use the first instruction supply scheme or the second instruction supply scheme. 
     
     
         17 . The apparatus according to  claim 16 , wherein for a given set of instructions, the second execution circuitry is configured to consume less energy when executing the set of instructions than the first execution circuitry;
 when using the second instruction supply scheme, the instruction supply circuitry is configured to consume less energy than when using the first instruction supply scheme; and   the control circuitry is configured to select the first instruction supply scheme for instructions to be executed by the first execution circuitry and to select the second instruction supply scheme for instructions to be executed by the second execution circuitry.   
     
     
         18 . The apparatus according to  claim 10 , wherein for a given set of instructions, the second execution circuitry is configured to consume less energy when executing the set of instructions than the first execution circuitry;
 when using the second branch prediction scheme, the branch prediction circuitry is configured to consume less energy than when using the first branch prediction scheme; and   the apparatus comprises control circuitry to select which of the first and second branch prediction schemes to use for a given set of instructions;   wherein the control circuitry is configured to permit the first branch prediction scheme to be selected for instructions to be executed by the second execution circuitry or permit the second branch prediction scheme to be selected for instructions to be executed by the first execution circuitry.   
     
     
         19 . The apparatus according to  claim 1 , comprising at least one shared pipeline element used both for instructions executed by the first execution circuitry and for instructions executed by the second execution circuitry. 
     
     
         20 . The apparatus according to  claim 19 , wherein the at least one shared pipeline element comprises at least one of:
 at least one instruction cache to store instructions to be fetched for processing;   fetch circuitry configured to fetch instructions for processing;   decode circuitry configured to decode instructions;   shared registers to store operands to be processed by the first execution circuitry and the second execution circuitry;   writeback circuitry to write data to registers in response to instructions executed by the first execution circuitry and the second execution circuitry;   a data cache to store data accessible in response to instructions executed by the first execution circuitry and the second execution circuitry;   status registers to store status information indicative of a status of the first execution circuitry or the second execution circuitry; and   configuration registers to store configuration information for configuring operation of the first execution circuitry or the second execution circuitry.   
     
     
         21 . A method comprising:
 selecting one of first and second execution circuitry of a processing pipeline for executing a group of instructions, the first and second execution circuitry having different performance or energy consumption characteristics; and   selecting one of first and second instruction supply schemes for supplying instructions to be processed by the selected one of the first and second execution circuitry, wherein the first and second instruction supply schemes have different performance or energy consumption characteristics.   
     
     
         22 . An apparatus comprising:
 a processing pipeline comprising first and second execution circuitry to execute instructions, wherein for at least one group of instructions, both the first and second execution circuitry are capable of executing said at least one group of instructions, and the first and second execution circuitry have different performance or energy consumption characteristics when executing said at least one group of instructions; and   shared architectural state storage circuitry accessible to both the first execution circuitry and the second execution circuitry;   wherein the shared architectural state storage circuitry comprises a plurality of a registers to store operands for processing by the first and second execution circuitry.   
     
     
         23 . The apparatus according to  claim 22 , wherein the shared architectural state storage circuitry comprises at least one of:
 status registers to store status information indicative of a status of the first execution circuitry or the second execution circuitry; and   configuration registers to store configuration information for configuring operation of the first execution circuitry or the second execution circuitry.   
     
     
         24 . The apparatus according to  claim 23 , wherein the status information comprises at least one of:
 a program counter indicative of a next instruction to be executed by the first execution circuitry or the second execution circuitry; and   condition information indicative of a current condition of the first execution circuitry or the second execution circuitry.   
     
     
         25 . The apparatus according to  claim 23 , wherein on switching execution from one of the first and second execution circuitry to the other of the first and second execution circuitry, the other of the first and second execution circuitry is configured to continue execution of instructions using architectural state data stored in the shared architectural state storage circuitry as a result of previous instructions executed by said one of the first and second execution circuitry. 
     
     
         26 . A method comprising:
 processing instructions with a processing pipeline comprising first and second execution circuitry, wherein for at least one group of instructions, both the first and second execution circuitry are capable of executing said at least one group of instructions, and the first and second execution circuitry have different performance or energy consumption characteristics when executing said at least one group of instructions; and   accessing shared architectural state storage circuitry accessible to both the first execution circuitry and the second execution circuitry;   wherein the shared architectural state storage circuitry comprises a plurality of a registers to store operands for processing by the first and second execution circuitry.   
     
     
         27 . An apparatus comprising:
 a processing pipeline comprising first and second execution circuitry to execute instructions, wherein for at least one group of instructions, both the first and second execution circuitry are capable of executing said at least one group of instructions, and the first and second execution circuitry have different performance or energy consumption characteristics when executing said at least one group of instructions; and   control circuitry to classify groups of instructions as first groups of instructions to be executed on the first execution circuitry or second groups of instructions to be executed on the second execution circuitry;   wherein the processing pipeline supports execution of at least one of said first groups of instructions on the first execution circuitry in parallel with execution of at least one of said second groups of instructions on the second execution circuitry.   
     
     
         28 . The apparatus according to  claim 27 , wherein the control circuitry is configured to monitor at least one performance metric during execution of a group of instructions, and to classify the group of instructions as one of the first groups or one of the second groups in dependence on said at least one performance metric. 
     
     
         29 . The apparatus according to  claim 27 , wherein the processing pipeline has a first processing mode permitting execution of at least one of said first groups of instructions on the first execution circuitry in parallel with execution of at least one of said second groups of instructions on the second execution circuitry. 
     
     
         30 . The apparatus according to  claim 29 , wherein the processing pipeline has a second processing mode permitting execution of instructions on one of said first and second execution circuitry at a time. 
     
     
         31 . The apparatus according to  claim 31 , comprising a configuration storage element to store configuration information specifying whether the processing pipeline is to operate in the first processing mode or the second processing mode. 
     
     
         32 . A method comprising:
 classifying groups of instructions as first groups to be executed on first execution circuitry of a processing pipeline and second groups to be executed on second execution circuitry of the processing pipeline, wherein for at least one group of instructions, both the first and second execution circuitry are capable of executing said at least one group of instructions, and the first and second execution circuitry have different performance or energy consumption characteristics when executing said at least one group of instructions; and   executing at least one of said first groups of instructions on the first execution circuitry in parallel with executing at least one of said second groups of instructions on the second execution circuitry.