US2016351733A1PendingUtilityA1

Dry etch method for texturing silicon and device

Assignee: IBMPriority: Jun 1, 2015Filed: Jun 1, 2015Published: Dec 1, 2016
Est. expiryJun 1, 2035(~8.8 yrs left)· nominal 20-yr term from priority
H01L 31/036H01L 31/208H01L 31/02363H10F 77/1692H10F 77/703H10F 77/147H10F 77/16H10F 71/128H10F 71/121H10F 71/10H10F 10/166H10F 77/707Y02E10/50Y02E10/547
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Claims

Abstract

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Claims

exact text as granted — not AI-modified
1 .- 14 . (canceled) 
     
     
         15 . A photovoltaic device, comprising:
 a textured silicon substrate including pyramidal shaped recesses formed in a surface thereof, the pyramidal shaped recesses including exposed (111) silicon surfaces;   a junction layer formed in accordance with the textured silicon substrate;   a first electrode layer formed in contact with the silicon substrate; and   a second electrode layer formed over the junction layer.   
     
     
         16 . The device as recited in  claim 15 , wherein the pyramidal shaped recesses are formed by exposing the silicon wafer to cracked sulfur species to etch the wafer to expose the (111) silicon surfaces. 
     
     
         17 . The device as recited in  claim 15 , wherein the pyramidal shaped recesses are randomly located across the surface. 
     
     
         18 . The device as recited in  claim 15 , wherein the pyramidal shaped recesses formed in the wafer have a depth of between about 10 nm and about 300 nm. 
     
     
         19 . The device as recited in  claim 15 , wherein the pyramidal shaped recesses formed in the wafer have a size of between about 20 nm and about 100 nm. 
     
     
         20 . The device as recited in  claim 15 , wherein the junction layer include one of a p-i-n stack, n-i-p stack, a p-n junction or n-p junction.

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