Semiconductor structure

Abstract

A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a dielectric layer disposed on a substrate, wherein the dielectric layer has at least a dishing from a first top surface; and   a shrinkable layer being a flowable chemical vapor deposition layer covering the dielectric layer, wherein the shrinkable layer has a second top surface and the whole second top surface is a flat top surface.   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein the dielectric layer has a trench, and a metal gate and a cap layer are stacked in the trench from bottom to top. 
     
     
         3 . The semiconductor structure according to  claim 2 , wherein the cap layer has at least a dishing. 
     
     
         4 . The semiconductor structure according to  claim 2 , wherein the dielectric layer comprises an oxide layer and the cap layer comprises a nitride layer. 
     
     
         5 . The semiconductor structure according to  claim 1 , wherein the dielectric layer comprises an inter-level dielectric layer. 
     
     
         6 . The semiconductor structure according to  claim 1 , wherein the shrinkable layer comprises an oxide layer. 
     
     
         7 . The semiconductor structure according to  claim 1 , wherein the dishing has a depth, and the shrinkable layer has a thickness larger than the depth.