Low temperature polycrystalline silicon thin film and method of producing the same, array substrate and display apparatus

Abstract

A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.

What is claimed is: 
     
         1 . A method for producing a low temperature polycrystalline silicon thin film, comprising steps of:
 providing a substrate;   forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and   performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film,   wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate,   wherein during the laser annealing, the amorphous silicon thin film is cooled more quickly in a first area with the patterns of the thermal conduction and electrical insulation layer than a second area without the patterns of the thermal conduction and electrical insulation layer.   
     
     
         2 . The method according to  claim 1 ,
 wherein the thermal conduction and electrical insulation layer is made of any one of aluminum nitride, boron nitride, aluminum oxide, and magnesium oxide.   
     
     
         3 . The method according to  claim 1 ,
 wherein the thermal conduction and electrical insulation layer comprises circular patterns, rectangular patterns or strip patterns evenly distributed on the substrate.   
     
     
         4 . The method according to  claim 3 ,
 wherein the circular pattern, the rectangular pattern or the strip pattern has a size within a range of 0.1 μm˜1 μm.   
     
     
         5 . The method according to  claim 4 ,
 wherein the size of the circular pattern, the rectangular pattern or the strip pattern is set as 0.5 μm.   
     
     
         6 . The method according to  claim 1 ,
 wherein the thermal conduction and electrical insulation layer is formed by spray coating, or by magnetron sputtering and exposure etching.   
     
     
         7 . A thin film transistor, comprising an active layer formed by a polycrystalline silicon thin film, wherein the polycrystalline silicon thin film is produced by a method according to  claim 1 . 
     
     
         8 . The thin film transistor according to  claim 7 ,
 wherein the buffer layer and the thermal conduction and electrical insulation layer are formed below the active layer of the thin film transistor.   
     
     
         9 . An array substrate comprising the thin film transistor according to  claim 7 . 
     
     
         10 . A display apparatus comprising the array substrate according to  claim 9 .