Semiconductor device

Abstract

A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

1 . A semiconductor device comprising:
 a substrate;   an insulator over the substrate; and   a memory cell string comprising a plurality of transistors connected in series,   wherein the memory cell string is provided on a side surface of the insulator, and   wherein the plurality of transistors each overlap with each other in a direction perpendicular to a top surface of the substrate.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the plurality of transistors each comprise a gate insulator and a gate electrode,   wherein the gate insulator comprises a first insulator, a second insulator, and a charge accumulation layer, and   wherein the charge accumulation layer is positioned between the first insulator and the second insulator.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the plurality of transistors each comprise an oxide semiconductor. 
     
     
         4 . The semiconductor device according to  claim 3 , wherein the oxide semiconductor comprises indium, an element M (aluminum, gallium, yttrium, or tin), and zinc. 
     
     
         5 . The semiconductor device according to  claim 1  further comprising a first transistor and a second transistor over the substrate,
 wherein a source terminal of the first transistor is electrically connected to a first terminal of the memory cell string, and 
 wherein a drain terminal of the second transistor is electrically connected to a second terminal of the memory cell string. 
 
     
     
         6 . The semiconductor device according to  claim 5 , wherein the first transistor and the second transistor each comprise single crystal silicon. 
     
     
         7 . The semiconductor device according to  claim 5 , wherein the first transistor and the second transistor each are between the substrate and the insulator. 
     
     
         8 . A semiconductor device comprising:
 a substrate;   an insulator over the substrate; and   a plurality of memory cell strings, the plurality of memory cell strings each comprise a plurality of transistors connected in series,   wherein the plurality of memory cell strings each are provided on a side surface of the insulator, and   wherein the plurality of transistors of one memory cell strings each overlap with each other in a direction perpendicular to a top surface of the substrate.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the plurality of transistors each comprise a gate insulator and a gate electrode,   wherein the gate insulator comprises a first insulator, a second insulator, and a charge accumulation layer, and   wherein the charge accumulation layer is positioned between the first insulator and the second insulator.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein the plurality of transistors each comprise an oxide semiconductor. 
     
     
         11 . The semiconductor device according to  claim 10 , wherein the oxide semiconductor comprises indium, an element M (aluminum, gallium, yttrium, or tin), and zinc. 
     
     
         12 . The semiconductor device according to  claim 10  further comprising a first transistor and a second transistor over the substrate,
 wherein a source terminal of the first transistor is electrically connected to a first terminal of each of the plurality of memory cell strings, and 
 wherein a drain terminal of the second transistor is electrically connected to a second terminal of each of the plurality of memory cell strings. 
 
     
     
         13 . The semiconductor device according to  claim 12 , wherein the first transistor and the second transistor each comprise single crystal silicon. 
     
     
         14 . The semiconductor device according to  claim 12 , wherein the first transistor and the second transistor each are between the substrate and the insulator.