Clock signal generating circuit, gate driving circuit, display panel and display device

Abstract

A clock signal generating circuit, a gate driving circuit, a display panel and a display device are disclosed. A first clock signal terminal inputs a first clock signal to a selection module. A second clock signal terminal inputs a second clock signal to the selection module. The selection module couples a high level signal input terminal to an output terminal or disconnects the high level signal input terminal from the output terminal according to the first clock signal, and couples a low level signal input terminal to the output terminal or disconnects the low level signal input terminal from the output terminal according to the second clock signal. The selection module couples the high level signal input terminal and the low level signal input terminal alternately to the output terminal, so that the output terminal outputs a target clock signal.

What is claimed is: 
     
         1 . A clock signal generating circuit, comprising a selection module, a high level signal input terminal, a low level signal input terminal, a first clock signal terminal, a second clock signal terminal and an output terminal, wherein
 the first clock signal terminal inputs a first clock signal to the selection module;   the second clock signal terminal inputs a second clock signal to the selection module;   the selection module couples the high level signal input terminal to the output terminal or disconnects the high level signal input terminal from the output terminal according to the first clock signal, and couples the low level signal input terminal to the output terminal or disconnects the low level signal input terminal from the output terminal according to the second clock signal; and   the selection module couples the high level signal input terminal and the low level signal input terminal alternately to the output terminal, so that the output terminal outputs a target clock signal.   
     
     
         2 . The clock signal generating circuit of  claim 1 , wherein the selection module comprises a first transistor and a second transistor,
 a gate of the first transistor is connected with the first clock signal terminal, a source of the first transistor is connected with the high level signal input terminal, and a drain of the first transistor is connected with the output terminal, and   a gate of the second transistor is connected with the second clock signal terminal, a source of the second transistor is connected with the low level signal input terminal, and a drain of the second transistor is connected with the output terminal.   
     
     
         3 . The clock signal generating circuit of  claim 1 , wherein a high level signal inputted from the high level signal input terminal and a low level signal inputted from the low level signal input terminal are direct current signals. 
     
     
         4 . The clock signal generating circuit of  claim 1 , wherein the first clock signal inputted from the first clock signal terminal and the second clock signal inputted from the second clock signal terminal have opposite levels at any time. 
     
     
         5 . The clock signal generating circuit of  claim 4 , wherein the target clock signal has a waveform the same as that of the first clock signal or the second clock signal. 
     
     
         6 . A gate driving circuit, comprising the clock signal generating circuit of  claim 1 , and multiple stages of shift registers. 
     
     
         7 . The gate driving circuit of  claim 6 , wherein the gate driving circuit comprises a plurality of the clock signal generating circuits, each of which is connected to a part of the shift registers. 
     
     
         8 . The gate driving circuit of  claim 7 , wherein the number of the clock signal generating circuits is two, and the two clock signal generating circuits are respectively located at an upper end and a lower end of one side of a display panel on which the shift registers are provided, and are respectively connected with the multiple stages of shift registers in an upper part of the display panel and the multiple stages of shift registers in a lower part of the display panel. 
     
     
         9 . The gate driving circuit of  claim 6 , wherein two ends of every row of pixels on the display panel are connected with one stage of shift registers on corresponding two sides, respectively. 
     
     
         10 . The gate driving circuit of  claim 9 , wherein a plurality of the clock signal generating circuits are provided on each of two opposite sides of the display panel on which the multiple stages of shift registers are provided, and each clock signal generating circuit is connected with a part of the shift registers on a corresponding side. 
     
     
         11 . The gate driving circuit of  claim 10 , wherein the number of the clock signal generating circuits is four, the four clock signal generating circuits are respectively provided in four corners of the display panel, each of the clock signal generating circuits located in the lower part is connected with the multiple stages of shift registers located in a lower part of a corresponding side of the display panel, and each of the clock signal generating circuits located in the upper part is connected with the multiple stages of shift registers located in an upper part of a corresponding side of the display panel. 
     
     
         12 . A display panel, comprising the gate driving circuit of  claim 6 . 
     
     
         13 . A display device, comprising the display panel of  claim 12 .