Shift register unit, shift register, gate driving circuit and display device

Abstract

The shift register unit includes a first module, a second module and a control module, where the first module including a first control transistor is configured to make an output terminal of the shift register unit in a current stage output a high level signal, where a gate electrode of the first control transistor is connected to the control module, a first electrode thereof is connected to a high level signal input terminal, a second electrode thereof is connected to the output terminal; the control module is configured to control on and off states of the first control transistor; and the second module including a second control transistor is configured to make the output terminal of the shift register unit in the current stage output a low level signal, where a gate electrode and a first electrode of the second control transistor are both connected to a low level signal input terminal, and a second electrode thereof is connected to the output terminal.

1 . A shift register unit, comprising a first module, a second module and a control module, wherein the first module comprising a first control transistor is configured to make an output terminal of the shift register unit in a current stage output a high level signal, wherein a gate electrode of the first control transistor is connected to the control module, a first electrode of the first control transistor is connected to a high level signal input terminal, a second electrode of the first control transistor is connected to the output terminal of the shift register unit in the current stage;
 the control module is configured to control on and off states of the first control transistor; and   the second module comprising a second control transistor is configured to make the output terminal of the shift register unit in the current stage output a low level signal, wherein a gate electrode and a first electrode of the second control transistor are both connected to a low level signal input terminal, and a second electrode of the second control transistor is connected to the output terminal of the shift register unit in the current stage.   
     
     
         2 . The shift register unit according to  claim 1 , wherein the control module comprises an initial signal module, a first capacitor and a first control module and a second control module connected with the first capacitor in parallel;
 wherein the initial signal module is configured to provide an initial signal to the first capacitor, the first control module and the second control module;   a first end of the first capacitor is connected to the initial signal module, and a second end of the first capacitor is connected to the gate electrode of the first control transistor;   the first control module is configured to control on and off states of the first control transistor based on the initial signal and a first clock signal input into a first clock signal input terminal; and   the second control module is configured to control on and off states of the first control transistor based on the initial signal and a second clock signal input into a second clock signal input terminal.   
     
     
         3 . The shift register unit according to  claim 2 , wherein the initial signal module comprises a signal control transistor, wherein a gate electrode of the signal control transistor is connected to the first clock signal input terminal, a first electrode of the signal control transistor is connected to an initial signal input terminal, and a second electrode of the signal control transistor is connected to the first end of the first capacitor, the first control module and the second control module. 
     
     
         4 . The shift register unit according to  claim 3 , wherein the first control module comprises a second capacitor, a first transistor, a second transistor and a third transistor;
 wherein a gate electrode and a first electrode of the first transistor are both connected to the first clock signal input terminal, a second electrode of the first transistor is connected to a second electrode of the second transistor and a gate electrode of the third transistor;   a gate electrode of the second transistor is connected to the second electrode of the signal control transistor, a first electrode of the second transistor is connected to the high level signal input terminal, and the second electrode of the second transistor is connected to a gate electrode of the third transistor; and   the gate electrode of the third transistor is connected to a first end of the second capacitor, a second end of the second capacitor is connected to the high level signal input terminal, a first electrode of the third transistor is connected to the high level signal input terminal, and a second electrode of the third transistor is connected to the gate electrode of the first control transistor and the second end of the first capacitor.   
     
     
         5 . The shift register unit according to  claim 4 , wherein the second control module comprises a fourth transistor, wherein a gate electrode of the fourth transistor is connected to the second electrode of the signal control transistor and the first end of the first capacitor, a first electrode of the fourth transistor is connected to the second clock signal input terminal, and a second electrode of the fourth transistor is connected to the gate electrode of the first control transistor and the second end of the first capacitor. 
     
     
         6 . A shift register, comprising multiple stages of the shift register unit according to  claim 1 . 
     
     
         7 . A gate driving circuit, comprising the shift register according to  claim 6 . 
     
     
         8 . A display device, comprising a gate electrode and the gate driving circuit according to  claim 7 . 
     
     
         9 . The shift register according to  claim 6 , wherein the control module comprises an initial signal module, a first capacitor and a first control module and a second control module connected with the first capacitor in parallel;
 wherein the initial signal module is configured to provide an initial signal to the first capacitor, the first control module and the second control module;   a first end of the first capacitor is connected to the initial signal module, and a second end of the first capacitor is connected to the gate electrode of the first control transistor;   the first control module is configured to control on and off states of the first control transistor based on the initial signal and a first clock signal input into a first clock signal input terminal; and   the second control module is configured to control on and off states of the first control transistor based on the initial signal and a second clock signal input into a second clock signal input terminal.   
     
     
         10 . The shift register according to  claim 9 , wherein the initial signal module comprises a signal control transistor, wherein a gate electrode of the signal control transistor is connected to the first clock signal input terminal, a first electrode of the signal control transistor is connected to an initial signal input terminal, and a second electrode of the signal control transistor is connected to the first end of the first capacitor, the first control module and the second control module. 
     
     
         11 . The shift register according to  claim 10 , wherein the first control module comprises a second capacitor, a first transistor, a second transistor and a third transistor;
 wherein a gate electrode and a first electrode of the first transistor are both connected to the first clock signal input terminal, a second electrode of the first transistor is connected to a second electrode of the second transistor and a gate electrode of the third transistor;   a gate electrode of the second transistor is connected to the second electrode of the signal control transistor, a first electrode of the second transistor is connected to the high level signal input terminal, and the second electrode of the second transistor is connected to a gate electrode of the third transistor; and   the gate electrode of the third transistor is connected to a first end of the second capacitor, a second end of the second capacitor is connected to the high level signal input terminal, a first electrode of the third transistor is connected to the high level signal input terminal, and a second electrode of the third transistor is connected to the gate electrode of the first control transistor and the second end of the first capacitor.   
     
     
         12 . The shift register according to  claim 11 , wherein the second control module comprises a fourth transistor, wherein a gate electrode of the fourth transistor is connected to the second electrode of the signal control transistor and the first end of the first capacitor, a first electrode of the fourth transistor is connected to the second clock signal input terminal, and a second electrode of the fourth transistor is connected to the gate electrode of the first control transistor and the second end of the first capacitor.