Semiconductor device and method for manufacturing semiconductor device
Abstract
A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
Claims
exact text as granted — not AI-modified1 . A semiconductor device comprising:
an electron trap layer between a first semiconductor and a gate electrode; and an electrode electrically connected to the first semiconductor, wherein the electron trap layer includes crystallized hafnium oxide, and wherein the electron trap layer is configured to trap electrons by setting a potential of the gate electrode higher than a potential of the electrode.
2 . The semiconductor device according to claim 1 , wherein the electron trap layer includes electron trap states.
3 . The semiconductor device according to claim 1 , wherein the crystallized hafnium oxide is monoclinic.
4 . The semiconductor device according to claim 1 , wherein the electrode is either a source electrode or a drain electrode.
5 . The semiconductor device according to claim 1 , further comprising:
a second semiconductor; and a third semiconductor, wherein the first semiconductor is between the second semiconductor and the third semiconductor, wherein the second semiconductor is between the first semiconductor and the gate electrode, and wherein the third semiconductor is between the first semiconductor and the electron trap layer.
6 . The semiconductor device according to claim 1 , wherein the potential of the gate electrode is lower than a maximum potential that is used in the semiconductor device.
7 . The semiconductor device according to claim 1 , wherein the first semiconductor is an oxide semiconductor.
8 . A display device comprising the semiconductor device according to claim 1 .
9 . An electronic device comprising the semiconductor device according to claim 1 .
10 . A semiconductor device comprising:
an electron trap layer between a first semiconductor and a gate electrode; and a metal electrode in direct contact with the first semiconductor, a second semiconductor; and a third semiconductor, wherein the first semiconductor is between the second semiconductor and the third semiconductor, wherein the second semiconductor is between the first semiconductor and the gate electrode, wherein the third semiconductor is between the first semiconductor and the electron trap layer, wherein the metal electrode is either a source electrode or a drain electrode, wherein the electron trap layer includes crystallized hafnium oxide, and wherein the electron trap layer is configured to trap electrons by setting a potential of the gate electrode higher than a potential of the metal electrode.
11 . The semiconductor device according to claim 10 , wherein the electron trap layer includes electron trap states.
12 . The semiconductor device according to claim 10 , wherein the crystallized hafnium oxide is monoclinic.
13 . The semiconductor device according to claim 10 , wherein the potential of the gate electrode is lower than a maximum potential that is used in the semiconductor device.
14 . The semiconductor device according to claim 10 , wherein the first semiconductor is an oxide semiconductor.
15 . A display device comprising the semiconductor device according to claim 10 .
16 . An electronic device comprising the semiconductor device according to claim 10 .Join the waitlist — get patent alerts
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