US2016343870A1PendingUtilityA1

Semiconductor device and method for manufacturing semiconductor device

Assignee: SEMICONDUCTOR ENERGY LABPriority: Sep 4, 2013Filed: Aug 8, 2016Published: Nov 24, 2016
Est. expirySep 4, 2033(~7.1 yrs left)· nominal 20-yr term from priority
H10P 95/70H10P 52/00H10P 50/285H10P 50/283H10P 50/267H10P 50/20H10P 14/69392H10P 14/6927H10P 14/6336H10P 14/6329H10P 14/692H10D 64/01342H10D 64/011H10D 64/037H10D 99/00H10D 86/423H10D 86/60H10D 64/691H10D 62/80H10D 30/6757H10D 30/6756H10D 30/6739H10D 30/6734H10D 30/673H10D 30/69H10D 30/6755H01L 21/465H01L 29/792H01L 21/02266H01L 29/66969H01L 29/517H01L 21/02181H01L 21/02274H01L 21/0214H01L 27/1225H01L 29/24H01L 29/7869H01L 29/4908H01L 21/441
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Claims

Abstract

A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 an electron trap layer between a first semiconductor and a gate electrode; and   an electrode electrically connected to the first semiconductor,   wherein the electron trap layer includes crystallized hafnium oxide, and   wherein the electron trap layer is configured to trap electrons by setting a potential of the gate electrode higher than a potential of the electrode.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the electron trap layer includes electron trap states. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the crystallized hafnium oxide is monoclinic. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the electrode is either a source electrode or a drain electrode. 
     
     
         5 . The semiconductor device according to  claim 1 , further comprising:
 a second semiconductor; and   a third semiconductor,   wherein the first semiconductor is between the second semiconductor and the third semiconductor,   wherein the second semiconductor is between the first semiconductor and the gate electrode, and   wherein the third semiconductor is between the first semiconductor and the electron trap layer.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein the potential of the gate electrode is lower than a maximum potential that is used in the semiconductor device. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the first semiconductor is an oxide semiconductor. 
     
     
         8 . A display device comprising the semiconductor device according to  claim 1 . 
     
     
         9 . An electronic device comprising the semiconductor device according to  claim 1 . 
     
     
         10 . A semiconductor device comprising:
 an electron trap layer between a first semiconductor and a gate electrode; and   a metal electrode in direct contact with the first semiconductor,   a second semiconductor; and   a third semiconductor,   wherein the first semiconductor is between the second semiconductor and the third semiconductor,   wherein the second semiconductor is between the first semiconductor and the gate electrode,   wherein the third semiconductor is between the first semiconductor and the electron trap layer,   wherein the metal electrode is either a source electrode or a drain electrode,   wherein the electron trap layer includes crystallized hafnium oxide, and   wherein the electron trap layer is configured to trap electrons by setting a potential of the gate electrode higher than a potential of the metal electrode.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein the electron trap layer includes electron trap states. 
     
     
         12 . The semiconductor device according to  claim 10 , wherein the crystallized hafnium oxide is monoclinic. 
     
     
         13 . The semiconductor device according to  claim 10 , wherein the potential of the gate electrode is lower than a maximum potential that is used in the semiconductor device. 
     
     
         14 . The semiconductor device according to  claim 10 , wherein the first semiconductor is an oxide semiconductor. 
     
     
         15 . A display device comprising the semiconductor device according to  claim 10 . 
     
     
         16 . An electronic device comprising the semiconductor device according to  claim 10 .

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