Multi-layer gate dielectric

Abstract

A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.

What is claimed is: 
     
         1 . An apparatus comprising:
 a gate electrode having a gate length; and   a gate dielectric adjacent to the gate electrode, wherein the gate dielectric comprises of at least two dielectric layers including a first dielectric layer and a second dielectric layer, wherein a total thickness of the gate dielectric is less than one third of the gate length of the gate electrode.   
     
     
         2 . The apparatus of  claim 1 , wherein the first dielectric layer is closer to a substrate than the second dielectric layer. 
     
     
         3 . The apparatus of  claim 1 , wherein the second dielectric layer is closer to the gate electrode than the first dielectric layer. 
     
     
         4 . The apparatus of  claim 1 , wherein the first dielectric layer comprises a material selected from a group consisting of: HfO 2 , ZrO 2 , BaI, La2O 3 , and Y 2 O 3 . 
     
     
         5 . The apparatus of  claim 1 , wherein the second dielectric layer comprises a material selected from a group consisting of: BaSrTiO 3  and PbZrTiO 3 . 
     
     
         6 . The apparatus of  claim 1 , wherein the gate electrode is one of: polysilicon or metal. 
     
     
         7 . The apparatus of  claim 1 , wherein the gate dielectric comprises a third dielectric layer adjacent to the second dielectric layer and the gate electrode. 
     
     
         8 . The apparatus of  claim 7 , wherein the third dielectric layer comprises a material selected from a group consisting of: HfO 2 , ZrO 2 , BaI, La2O 3 , and Y2O 3 . 
     
     
         9 . The apparatus of  claim 7 , wherein the third dielectric layer is formed of a material which is same as material of the first dielectric layer, but different from a material of the second dielectric layer. 
     
     
         10 . The apparatus of  claim 1 , wherein the first dielectric layer has a dielectric constant lower than a dielectric constant of the second dielectric layer. 
     
     
         11 . The apparatus of  claim 1 , wherein the first dielectric layer comprises material that has a heat of formation greater than heat of formation of SiO 2 . 
     
     
         12 . The apparatus of  claim 1  comprises a barrier layer sandwiched between the gate electrode and the gate dielectric. 
     
     
         13 . A semiconductor chip comprising:
 an integrated circuit having a plurality of transistors, wherein at least one of the transistors comprises:
 a substrate; 
 a gate dielectric disposed on the substrate, the gate dielectric comprising at least two dielectric layers including a first dielectric layer and a second dielectric layer, wherein the first and second dielectric layers comprises first and second metal oxides, respectively; 
 a gate electrode adjacent to the gate dielectric, wherein the gate electrode has a gate length which is greater than a total thickness of the gate dielectric; 
 a first diffusion region adjacent to the gate electrode; and 
 a second diffusion region adjacent to the gate electrode, wherein the first and second diffusion regions are formed in the substrate. 
   
     
     
         14 . The semiconductor chip of  claim 13 , wherein the first dielectric layer comprises material that has a heat of formation greater than heat of formation of SiO 2 . 
     
     
         15 . The semiconductor chip of  claim 13  comprises a barrier layer sandwiched between the gate electrode and the gate dielectric. 
     
     
         16 . The semiconductor chip of  claim 13 , wherein the first dielectric layer is closer to a substrate than the second dielectric layer. 
     
     
         17 . The semiconductor chip of  claim 13 , wherein the at least two dielectric layers form a vertical stack of layers. 
     
     
         18 . The semiconductor chip of  claim 13 , wherein the gate dielectric comprises a third dielectric layer adjacent to the second dielectric layer and the gate electrode. 
     
     
         19 . The semiconductor chip of  claim 18 , wherein the third dielectric layer is formed of a material which is same as material of the first dielectric layer, but different from a material of the second dielectric layer. 
     
     
         20 . The semiconductor chip of  claim 18 , wherein:
 the first dielectric layer comprises a material selected from a group consisting of: HfO 2 , ZrO 2 , BaI, La2O 3 , and Y2O 3 ;   the second dielectric layer comprises a material selected from a group consisting of: BaSrTiO 3  and PbZrTiO 3 ;   the third dielectric layer comprises a material selected from a group consisting of: HfO 2 , ZrO 2 , BaI, La2O 3 , and Y2O 3 ; and.   the gate electrode is one of: polysilicon or metal.