US2016343604A1PendingUtilityA1

Substrate structure with embedded layer for post-processing silicon handle elimination

47
Assignee: RF MICRO DEVICES INCPriority: May 22, 2015Filed: Mar 30, 2016Published: Nov 24, 2016
Est. expiryMay 22, 2035(~8.8 yrs left)· nominal 20-yr term from priority
Inventors:Julio C. CostaJan Edward Vandemeer
H10P 72/7434H10P 72/7422H10P 72/7416H10W 10/181H10P 90/1922H10P 90/1914H10P 72/74H10D 62/115H10D 62/83H10D 62/126H01L 29/0649H01L 21/68785H01L 29/16H01L 29/0692
47
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 a silicon handle layer;   a buried dielectric layer over the silicon handle layer, wherein the buried dielectric layer is not formed from silicon oxide;   an upper silicon oxide layer over the buried dielectric layer; and   a silicon epitaxy layer over the upper silicon oxide layer.   
     
     
         2 . The apparatus of  claim 1  further comprising a lower silicon oxide layer residing between the silicon handle layer and the buried dielectric layer. 
     
     
         3 . The apparatus of  claim 1  wherein the buried dielectric layer is formed from silicon nitride. 
     
     
         4 . The apparatus of  claim 1  wherein the silicon epitaxy layer has a higher resistivity than the silicon handle layer and the silicon epitaxy layer has lower harmonic generation than the silicon handle layer. 
     
     
         5 . The apparatus of  claim 1  wherein:
 the silicon epitaxy layer has a higher resistivity than the silicon handle layer; 
 the silicon epitaxy layer has lower harmonic generation than the silicon handle layer; and 
 the buried dielectric layer is formed from silicon nitride. 
 
     
     
         6 . The apparatus of  claim 1  wherein the resistivity of the silicon epitaxy layer is between 1 ohm/cm and 50 ohm/cm. 
     
     
         7 . The apparatus of  claim 1  wherein a thickness of the silicon epitaxy layer is between 100 Å and 2 μms. 
     
     
         8 . The apparatus of  claim 1  wherein a thickness of the silicon handle layer is thicker than 100 μms and a thickness of the silicon epitaxy layer is between 100 Å and 2 μms. 
     
     
         9 . The apparatus of  claim 2  wherein a thickness of the lower silicon oxide layer is between 200 Å and 5000 Å, a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å and a thickness of the buried dielectric layer is between 300 Å and 2000 Å. 
     
     
         10 . The apparatus of  claim 2  wherein a thickness of the silicon handle layer is thicker than 100 μms, a thickness of the silicon epitaxy layer is between 100 Å and 2 μms, a thickness of the lower silicon oxide layer is between 200 Å and 5000 Å, a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å, and a thickness of the buried dielectric layer is between 300 Å and 2000 Å. 
     
     
         11 . The apparatus of  claim 1  wherein the silicon epitaxy layer has a ground surface that is opposite the upper silicon oxide layer. 
     
     
         12 . An apparatus comprising:
 a buried dielectric layer over the transfer substrate layer, wherein the buried dielectric layer is not formed from silicon oxide;   an upper silicon oxide layer over the buried dielectric layer; and   an electronic layer over the second silicon oxide layer.   
     
     
         13 . The apparatus of  claim 12  further comprising a transfer substrate layer that does not comprise single crystal silicon. 
     
     
         14 . The apparatus of  claim 13  wherein the transfer substrate layer is formed from one of a group consisting of polymer, ceramic, and gallium arsenide. 
     
     
         15 . The apparatus of  claim 13  wherein a thickness of the transfer substrate layer is between 50 μms and 2500 μms. 
     
     
         16 . The apparatus of  claim 13  further comprising a lower silicon oxide layer residing between the transfer substrate layer and the buried dielectric layer. 
     
     
         17 . The apparatus of  claim 12  wherein the buried dielectric layer is formed from silicon nitride. 
     
     
         18 . The apparatus of  claim 12  wherein a thickness of the electronic layer is between 2 μms and 10 μms. 
     
     
         19 . The apparatus of  claim 12  wherein a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å, and a thickness of the buried dielectric layer is between 300 Å and 2000 Λ. 
     
     
         20 . The apparatus of  claim 16  wherein a thickness of the electronic layer is between 2 μms and 10 μms, a thickness of the upper silicon oxide layer is between 200 Å and 5000 Å, a thickness of the buried dielectric layer is between 300 Å and 2000 Å, a thickness of the lower silicon oxide layer is between 200 Å and 5000 Å, and a thickness of the transfer substrate layer is between 50 μms and 2500 μms.

Join the waitlist — get patent alerts

Track US2016343604A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.