Providing vector sub-byte decompression functionality

Abstract

Processing to execute SIMD vector sub-byte decompression functionality includes copying a first two bytes into the least significant portion of a first vector element, a second two bytes into the most significant portion, and copying a third two bytes into the least significant portion of a second vector element, and a fourth two bytes into the most significant portion. Processing continues by shifting the first vector element by a first shift count and the second vector element by a second shift count. Processing continues with copying the first two bytes and the third two bytes from the shifted first and second vector elements into a first destination vector element, and the second two bytes and the fourth two bytes from the shifted first and second vector elements into a second destination vector element, to at least partially restore an original sub-byte order of the sub-byte elements.

What is claimed is: 
     
         1 . A processor comprising:
 a decoder to decode an instruction into a decoded instruction, wherein the instruction specifies a vector sub-byte decompression operation, a destination vector, and a source of sub-byte elements; and   logic circuitry of an execution unit operatively coupled to the decoder that, responsive to the decoded instruction, is to:
 copy, from the source, a first two bytes into a least significant portion of a first vector element, and a second two bytes into a most significant portion of the first vector element, the first two bytes containing a first sub-byte element and the second two bytes containing a second sub-byte element; 
 copy, from the source, a third two bytes into a least significant portion of a second vector element, and a fourth two bytes into a most significant portion of the second vector element, the third two bytes containing a third sub-byte element and the fourth two bytes containing a fourth sub-byte element; 
 shift the first vector element by a first shift count and the second vector element by a second shift count different than the first shift count; and 
 copy the first sub-byte and the third sub-byte from the shifted first and second vector elements into a first destination vector element, and the second sub-byte and the fourth sub-byte from the shifted first and second vector elements into a second destination vector element, to at least partially restore an original sub-byte order of the sub-byte elements. 
   
     
     
         2 . The processor of  claim 1 , wherein the first two bytes and second two bytes are the same as the third two bytes and fourth two bytes, respectively. 
     
     
         3 . The processor of  claim 1 , wherein the first sub-byte element and the second sub-byte element are of a first bit alignment, and wherein the third sub-byte element and the fourth sub-byte element are of a second bit alignment. 
     
     
         4 . The processor of  claim 3 , wherein the first two bytes contain a fifth sub-byte element of the first bit alignment, the second two bytes contain a sixth sub-byte element of the first bit alignment, the third two bytes contain a seventh sub-byte element of the second bit alignment, and the fourth two bytes contain an eighth sub-byte element of the second bit alignment. 
     
     
         5 . The processor of  claim 3 , wherein the logic circuitry is further to:
 shift the first vector element by the first shift count to align the first sub-byte element to a least significant bit of the least significant portion of the first vector element and to align the second sub-byte element to a least significant bit of the most significant portion of the first vector element; and   shift the second vector element by the second shift count to align the third sub-byte element to a least significant bit of the least significant portion of the second vector element and to align the fourth sub-byte element to a least significant bit of the most significant portion of the second vector element.   
     
     
         6 . The processor of  claim 5 , wherein the logic circuitry is further to:
 copy, from the source, a fifth two bytes of a third bit alignment into a least significant portion of a third vector element, and a sixth two bytes of the third bit alignment into a most significant portion of the third vector element, the fifth two bytes containing a fifth sub-byte element and the sixth two bytes containing a sixth sub-byte element;   copy from the source, a seventh two bytes of a fourth bit alignment into a least significant portion of a fourth vector element, and an eighth two bytes of the fourth bit alignment into a most significant portion of the fourth vector element, the seventh two bytes containing a seventh sub-byte element and the eighth two bytes containing an eighth sub-byte element;   shift the third vector element by a third shift count to align the fifth sub-byte element to a least significant bit of the least significant portion of the third vector element and to align the sixth sub-byte element to a least significant bit of the most significant portion of the third vector element;   shift the fourth vector element by a fourth shift count to align the seventh sub-byte element to a least significant bit of the least significant portion of the fourth vector element and to align the eighth sub-byte element to a least significant bit of the most significant portion of the fourth vector element; and   copy the fifth sub-byte and the seventh sub-byte from the shifted third and fourth vector elements into a first intermediate vector element, and the sixth sub-byte and the eighth sub-byte from the shifted third and fourth vector elements into a second intermediate vector element, to at least partially restore the original sub-byte order.   
     
     
         7 . The processor of  claim 1 , wherein the logic circuitry is further to:
 combine the first and second destination vector elements with vector elements of an intermediate vector, to populate the destination vector with the original sub-byte order of the sub-byte elements being restored; and   correct a number of most significant bits of a byte of the destination vector.   
     
     
         8 . The processor of  claim 7 , wherein the instruction further specifies a sub-byte element size, and wherein the logic circuitry is further to set k most significant bits to zero in the byte of the destination vector, to correct the number of most significant bits, wherein k is equal to eight minus the sub-byte element size. 
     
     
         9 . The processor of  claim 7 , wherein the instruction further specifies a sub-byte element size, and wherein the logic circuitry is further to set k most significant bits equal to a most significant bit of a sub-byte element in the byte of the destination vector, to correct the number of most significant bits, wherein k is equal to eight minus the sub-byte element size. 
     
     
         10 . The processor of  claim 1 , further comprising a memory to store the instruction, wherein the memory is one of a cache memory or a microcode storage memory. 
     
     
         11 . A non-transitory machine-readable medium to record functional descriptive material including one or more executable instructions, which when executed on behalf of a thread of a machine, causes the machine to perform operations comprising:
 copying a first and a second byte into a least significant portion of a first vector element, and a third and a fourth byte into a most significant portion of the first vector element, the first and the second byte containing a first sub-byte element, and the third and the fourth byte containing a second sub-byte element;   copying a fifth and a sixth byte into a least significant portion of a second vector element, and a seventh and an eighth byte into a most significant portion of the second vector element, the fifth and the sixth byte containing a third sub-byte element, and the seventh and the eight byte containing a fourth sub-byte element;   shifting the first vector element by a first shift count and the second vector element by a second shift count different than the first shift count; and   copying a byte from least significant portions of the shifted first and second vector elements into a first destination vector element and from most significant portions of the shifted first and second vector elements into a second destination vector element, to at least partially restore an original sub-byte order of sub-byte elements within a plurality of destination vector elements.   
     
     
         12 . The non-transitory machine-readable medium of  claim 11 , wherein the first sub-byte element and the second sub-byte element are of a first bit alignment, and wherein the third sub-byte element and the fourth sub-byte element are of a second bit alignment. 
     
     
         13 . The non-transitory machine-readable medium of  claim 12 , wherein the second byte contains a fifth sub-byte element of the first bit alignment, the fourth byte contains a sixth sub-byte element of the first bit alignment, the sixth byte contains a seventh sub-byte element of the second bit alignment, and the eighth byte contains an eighth sub-byte element of the second bit alignment. 
     
     
         14 . The non-transitory machine-readable medium of  claim 13 , wherein the one or more executable instructions, when executed on behalf of a thread of the machine, causes the machine to perform operations comprising copying another byte from least significant portions of the shifted first and second vector elements into a third destination vector element and from most significant portions of the shifted first and second vector elements into a fourth destination vector element, to at least partially restore an original sub-byte order of the sub-byte elements. 
     
     
         15 . The non-transitory machine-readable medium of  claim 11 , wherein the one or more executable instructions, when executed on behalf of a thread of the machine, causes the machine to perform operations comprising:
 combining the first and second destination vector elements with vector elements of an intermediate vector, to populate a destination vector with the original sub-byte order of the sub-byte elements being restored; and   correcting a number of bits of a byte of the destination vector.   
     
     
         16 . The non-transitory machine-readable medium of  claim 15 , wherein correcting the number of bits comprises setting k bits to zero in the byte of the destination vector, wherein k is an integer between one and seven, including one or seven. 
     
     
         17 . The non-transitory machine-readable medium of  claim 15 , wherein correcting the number of bits comprises setting k bits equal to a most significant bit of a sub-byte element in the byte of the destination vector, wherein k is equal to eight minus a size of the sub-byte elements. 
     
     
         18 . A processing system comprising:
 a system memory to hold one or more instructions specifying a vector sub-byte decompression operation from a source of sub-byte elements to a destination vector; and   a processor comprising a decoder and logic circuitry of an execution unit, wherein the decoder is to decode the one or more instructions specifying the vector sub-byte decompression operation, to generate one or more decoded instructions; and   wherein the logic circuitry is to, responsive to the one or more decoded instructions:
 copy, from the source, a first two bytes into a least significant portion of a first vector element, and a second two bytes into a most significant portion of the first vector element, the first two bytes containing a first sub-byte element and the second two bytes containing a second sub-byte element; 
 copy, from the source, a third two bytes into a least significant portion of a second vector element, and a fourth two bytes into a most significant portion of the second vector element, the third two bytes containing a third sub-byte element and the fourth two bytes containing a fourth sub-byte element; 
 shift the first vector element by a first shift count and the second vector element by a second shift count different than the first shift count; and 
 copy the first sub-byte and the third sub-byte from the shifted first and second vector elements into a first destination vector element, and the second sub-byte and the fourth sub-byte from the shifted first and second vector elements into a second destination vector element, to at least partially restore an original sub-byte order of the sub-byte elements. 
   
     
     
         19 . The system of  claim 18 , wherein the first sub-byte element and the second sub-byte element are of a first bit alignment, and wherein the third sub-byte element and the fourth sub-byte element are of a second bit alignment. 
     
     
         20 . The system of  claim 19 , wherein the first two bytes contain a fifth sub-byte element of the first bit alignment, the second two bytes contain a sixth sub-byte element of the first bit alignment, the third two bytes contain a seventh sub-byte element of the second bit alignment, and the fourth two bytes contain an eighth sub-byte element of the second bit alignment.