Array substrate and manufacturing method thereof

Abstract

A method of manufacturing an array substrate is disclosed. A first conductive pattern, a first insulating layer, a second conductive pattern, and a second insulating layer on a base substrate is successively formed. The second insulating layer and the first insulating layer are patterned with a double-tone mask. At least a half lap joint via hole in the second insulating layer, and at least a full lap joint via hole in both the first insulating layer and the second insulating layer is formed. The second conductive pattern corresponds to a part of the half lap joint via hole, and the first conductive pattern corresponds to the whole of the full lap joint via hole. A third conductivity pattern is formed on the surface of the second conductivity pattern and the first insulating layer and a fourth conductive pattern is formed on the surface of the first conductive pattern.

1 . An array substrate, comprising a base substrate with a plurality of pixel units formed on the base substrate, wherein:
 at least a first conductive pattern is formed on the base substrate and is covered by a first insulating layer,   at least a second conductive pattern is formed on the first insulating layer and is covered by a second insulating layer,   at least a third conductive pattern and a fourth conductive pattern are formed on the second insulating layer,   at least a half lap joint via hole is formed in the second insulating layer, and at least a full lap joint via hole is formed in the first insulating layer and the second insulating layer, the second conductive pattern corresponds to a part of the half lap joint via hole, the first conductive pattern corresponds to the whole of the full lap joint via hole; the third conductivity pattern is formed on the surface of the second conductivity pattern and the first insulating layer through the half lap joint via hole, and the fourth conductive pattern is formed on the surface of the first conductive pattern through the full lap joint via hole.   
     
     
         2 . The array substrate according to  claim 1 , wherein:
 the first conductive pattern is a gate line pad region, and the fourth conductive pattern comprises a gate line pad region connection line.   
     
     
         3 . The array method according to  claim 1 , wherein:
 the second conductive pattern comprises a drain electrode, and the third conductive pattern comprises a pixel electrode.   
     
     
         4 . The array method according to  claim 1 , wherein:
 the second conductive pattern comprises a gate line pad region, and third conductive pattern comprises a data line pad region connection line.   
     
     
         5 . The array method according to  claim 1 , wherein:
 The second conductive pattern comprises a data line, and the third conductive pattern comprises a data line bridging line.   
     
     
         6 . The array method according to  claim 1 , wherein:
 a data line pad region is formed on the first insulating layer, a full lap joint via hole is formed in the second insulating layer, a data line bridging line is formed on the second insulating layer, and the data line bridging line is formed on the surface of the data line via the full lap joint via hole.   
     
     
         7 . The array method according to  claim 1 , wherein:
 a data line is formed on the first insulating layer, a full lap joint via hole is formed in the second insulating layer, a data line bridging line is formed on the second insulating layer, and the data line bridging line is formed on the surface of the data line via the full lap joint via hole.