Method of fabricating semiconductor device

Abstract

A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

1 . A method of fabricating a semiconductor device, comprising:
 providing a substrate, the substrate including two first regions and a second region provided therebetween;   forming first patterns on the first regions, respectively, the first patterns and the substrate defining a stepwise portion at the second region;   forming second patterns on the first patterns, respectively, to form a dummy pattern at the stepwise portion of the second region; and   forming a material layer to cover the second patterns and the dummy pattern.   
     
     
         2 . The method of  claim 1 , wherein the dummy pattern and the second patterns include substantially common materials. 
     
     
         3 . (canceled) 
     
     
         4 . A method of fabricating a semiconductor device, comprising:
 providing a substrate including two cell regions and a non-cell region provided therebetween;   forming lower structures on the cell regions, respectively, the lower structures and the substrate defining a first stepwise portion at the non-cell region;   forming capacitors on the lower structures formed on the cell regions, wherein each of the capacitors is electrically separated from the lower structures, and each of the capacitors includes a first electrode, a dielectric layer, and a second electrode;   forming a plate electrode on the cell regions to form a first dummy pattern at the first stepwise portion, the plate electrode electrically coupling the second electrodes of the capacitors to each other; and   forming an insulating layer to cover the plate electrode and the first dummy pattern.   
     
     
         5 . (canceled) 
     
     
         6 . (canceled) 
     
     
         7 . (canceled) 
     
     
         8 . The method of  claim 4 , further comprising:
 forming an auxiliary structure on the non-cell region;   exposing the auxiliary structure to simultaneously form a first lower structure on the cell regions and form a first opening on the non-cell region; and   forming a second lower structure on the cell regions to form a second dummy pattern filling the first opening.   
     
     
         9 . The method of  claim 8 , wherein the first opening includes a hole-shaped structure or a line-shaped structure. 
     
     
         10 . The method of  claim 8 , wherein the second dummy pattern fills the first opening and has a shape corresponding to a shape of the first opening. 
     
     
         11 . The method of  claim 8 , wherein the second dummy pattern partially fills the first opening. 
     
     
         12 . The method of  claim 8 , wherein the second dummy pattern fills the first opening and includes an upward-protruding structure. 
     
     
         13 . The method of  claim 8 , wherein the auxiliary structure includes at least one of a photo key, an electrical test pattern, and a measurement site. 
     
     
         14 . The method of  claim 4 , further comprising,
 forming a photo key on the non-cell region;   forming a device isolation pattern on the cell regions and the non-cell region to define active patterns on the cell regions and active patterns on the non-cell region;   forming a plurality of transistors on the cell regions, each transistor including a gate electrode crossing active patterns of the cell regions, the active patterns including first and second impurity regions;   forming a first interlayered insulating layer on the cell regions and the non-cell region;   exposing the photo key and at least a portion of the device isolation pattern on the non-cell region;   patterning the first interlayered insulating layer of the cell regions to form first contact holes exposing the first impurity regions, the patterning being based on a photolithography process using the photo key;   etching the exposed portion of the device isolation pattern of the non-cell region to form a first opening;   filling the first contact holes with a first conductive layer to form first contact plugs; and   filling the first opening with the first conductive layer to form a second dummy pattern.   
     
     
         15 . The method of  claim 14 , wherein the forming of the plurality of transistors includes,
 forming recesses to cross the active patterns of the cell regions;   forming a gate insulating layer to conformally cover the recesses;   forming the gate electrodes to respectively fill lower portions of the recesses covered with the gate insulating layer;   forming capping patterns to respectively fill upper portions of the recesses; and   injecting impurities into portions of the active patterns to form the first and second impurity regions, the active patterns being exposed at both sides of each of the capping patterns.   
     
     
         16 . The method of  claim 14 , further comprising:
 forming bit lines on the cell regions to electrically couple the first contact plugs to each other;   forming a second interlayered insulating layer to cover the cell regions and the non-cell region;   exposing the photo key of the non-cell region;   patterning the first and second interlayered insulating layers to form second contact holes exposing the second impurity regions, the patterning the first and second interlayered   insulating layers being based on a photolithography process using the photo key;
 forming a dummy hole on the non-cell region; 
 filling the second contact holes with a second conductive layer to form second contact plugs; and 
 filling the dummy hole with the second conductive layer to form a third dummy pattern. 
   
     
     
         17 . The method of  claim 16 , wherein the second dummy pattern includes a pillar-shaped structure penetrating the first and second interlayered insulating layers. 
     
     
         18 . The method of  claim 16 , wherein the second dummy pattern includes a pillar portion and a cover portion, the pillar portion penetrating the first and second interlayered insulating layers, the cover portion being connected to the pillar portion, such that the pillar portion and the cover portion form a “T”-shaped section of the second dummy pattern. 
     
     
         19 . The method of  claim 16 , wherein the non-cell region includes a core/peripheral region, the core/peripheral region configured to enable electrical signal transmission from/to the cell regions, and
 the forming of the bit lines on the cell regions further comprises forming a core/peripheral gate electrode on the core/peripheral region.   
     
     
         20 . A method, comprising:
 forming a plurality of first patterns on respective first regions of a substrate, the substrate including a second region between the first regions, the first patterns and the substrate defining a first stepwise portion at the second region; and   forming a dummy pattern to at least partially fill the first stepwise portion.   
     
     
         21 . The method of  claim 20 , further comprising:
 forming a plurality of second patterns on respective first patterns of the plurality of first patterns such that the dummy pattern, the first patterns, and the second patterns define a second stepwise portion at the second region;   forming a material layer to cover at least the first patterns, the second patterns, and the dummy pattern, the material layer including a stepwise portion corresponding to the second stepwise portion, the material layer omitting another stepwise portion corresponding to the first stepwise portion based on the dummy pattern at least partially filling the first stepwise portion; and   polishing the material layer to form a uniform top surface of the material layer.   
     
     
         22 . The method of  claim 20 , wherein
 each first region is a cell region;   each second region is a non-cell region; and   each first pattern includes at least one of a device isolation pattern, an active pattern, a transistor, and a bit line.   
     
     
         23 . The method of  claim 22 , further comprising:
 forming capacitors on the first patterns, wherein each capacitor is electrically separated from the first patterns, and each capacitor includes a first electrode, a dielectric layer, and a second electrode; and   forming a plate electrode on the cell regions to form the dummy pattern, the plate electrode electrically coupling the second electrodes of the capacitors to each other.   
     
     
         24 . The method of  claim 21 , wherein the dummy pattern and the plurality of second patterns are formed simultaneously.