US2016336272A1PendingUtilityA1

Semiconductor Device Having Gold Metallization Structures

Assignee: INFINEON TECHNOLOGIES AUSTRIA AGPriority: Sep 19, 2014Filed: Jul 26, 2016Published: Nov 17, 2016
Est. expirySep 19, 2034(~8.2 yrs left)· nominal 20-yr term from priority
Inventors:Arno Zechmann
H10W 20/40H10W 20/4435H10W 20/4432H10W 20/089H10W 20/063H10W 20/057H10W 20/054H10W 20/049H10W 20/043H10W 20/43H10W 20/42H10W 20/033H10W 20/425H10W 72/073H01L 23/53252H01L 23/5226H01L 21/76873H01L 23/528H01L 21/76816H01L 21/76843H01L 21/76879
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Claims

Abstract

A semiconductor device includes a semiconductor substrate having first and second terminals of one or more semiconductor devices, first and second barrier metal regions electrically connected to the first and second terminals, respectively, and first and second gold metallization structures electrically connected to the first and second terminals via the first and second barrier metal regions, respectively. The first and second gold metallization structures contain diffused copper atoms. Interfaces between the first and second barrier metals and the first and second gold metallization structures, respectively, are substantially devoid of metallic copper.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate comprising first and second terminals of one or more semiconductor devices;   first and second barrier metal regions electrically connected to the first and second terminals, respectively; and   first and second gold metallization structures electrically connected to the first and second terminals via the first and second barrier metal regions, respectively;   wherein the first and second gold metallization structures comprise diffused copper atoms, and   wherein interfaces between the first and second barrier metals and the first and second gold metallization structures, respectively, are substantially devoid of metallic copper.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a width of the first and second gold metallization structures is less than 10 μm, and wherein a separation distance between the first and second gold metallization lines is less than 10 μm. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first terminal is a source terminal of a transistor, wherein the second terminal is a drain terminal of the transistor, and wherein the first and second gold metallization structures are electrically insulated from one another.

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