Silicon-glass hybrid interposer circuitry

Abstract

An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer.

What is claimed is: 
     
         1 . An interposer, comprising:
 a glass substrate;   a semiconductor layer formed on the glass substrate, wherein the semiconductor layer has a bottom surface that faces the glass substrate and a top surface;   a transistor formed at the top surface of the semiconductor layer; and   a dielectric layer formed over the transistor, wherein the dielectric layer and the glass substrate are formed from different materials.   
     
     
         2 . The interposer of  claim 1 , wherein the glass substrate includes sodium. 
     
     
         3 . The interposer of  claim 1 , wherein the glass substrate comprises Borofloat® glass. 
     
     
         4 . The interposer of  claim 1 , wherein the glass substrate comprises Pyrex® glass. 
     
     
         5 . The interposer of  claim 1 , wherein the semiconductor layer comprises a silicon layer, and wherein the glass substrate comprises a material that is different than the semiconductor layer. 
     
     
         6 . The interposer of  claim 1 , wherein the glass substrate has a bottom surface that is at least partially exposed. 
     
     
         7 . The interposer of  claim 1 , wherein the semiconductor layer exhibits a first signal transmission characteristic, and wherein the glass layer exhibits a second signal transmission characteristic that is better than the first signal transmission characteristic. 
     
     
         8 . The interposer of  claim 1 , further comprising:
 a through-interposer via formed through the semiconductor layer and the glass substrate; and   an insulating liner interposed between the through-interposer via and the semiconductor layer.   
     
     
         9 . The interposer of  claim 8 , wherein the through-interposer via directly contacts the glass substrate. 
     
     
         10 . The interposer of  claim 1 , further comprising:
 a bump metallization conductor formed directly on the glass substrate.   
     
     
         11 . The interposer of  claim 10 , further comprising:
 a bump formed directly on the bump metallization conductor.   
     
     
         12 . A method of fabricating a hybrid integrated circuit package interposer, comprising:
 forming a semiconductor layer on a glass substrate; and   after forming the semiconductor layer on the glass substrate, forming a transistor in the semiconductor layer, wherein the semiconductor layer exhibits a first signal transmission property, and wherein the glass substrate exhibits a second signal transmission property that is better than the first signal transmission property.   
     
     
         13 . The method of  claim 12 , wherein the glass substrate comprises material selected from the group consisting of: sodium, Borofloat® glass, and Pyrex® glass. 
     
     
         14 . The method of  claim 12 , wherein the glass layer exhibits better insertion loss than the semiconductor layer. 
     
     
         15 . The method of  claim 12 , further comprising:
 after forming the semiconductor layer on the glass substrate, forming a through hole in only the semiconductor layer but not the glass substrate.   
     
     
         16 . A multichip package, comprising:
 a glass substrate;   a silicon layer formed on the glass substrate;   a dielectric layer formed on the silicon layer, wherein the dielectric layer and the glass substrate are formed from different materials; and   an integrated circuit die mounted over the dielectric layer.   
     
     
         17 . The multichip package of  claim 16 , wherein the silicon layer is thinner than the glass substrate. 
     
     
         18 . The multichip package of  claim 16 , further comprising:
 a through-interposer via formed through the dielectric layer, the silicon layer, and the glass substrate.   
     
     
         19 . The multichip package of  claim 16 , further comprising:
 an additional integrated circuit die mounted over the dielectric layer.   
     
     
         20 . The multichip package of  claim 16 , further comprising:
 a package substrate to which the glass substrate is attached.