Dram-Type Device With Low Variation Transistor Peripheral Circuits, and Related Methods

Abstract

A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.

1 - 20 . (canceled) 
     
     
         21 . An integrated circuit, comprising:
 a body bias control circuit configured to generate body bias voltage from a bias supply voltage;   functional circuits having at least one transistor having a body coupled to receive the body bias voltage, wherein;   the functional circuits comprise a digital delay line circuit including at least a fine delay circuit having a plurality of delay stages arranged in series, each delay stage including the transistors; and   the body bias control circuit is a delay control circuit configured to apply different body biases to the transistors of the delay stages in response to a delay set value.   
     
     
         22 . An integrated circuit of  claim 21 , further comprising:
 a plurality of dynamic random access memory (DRAM) cells formed in the same substrate as the functional circuits, each DRAM cell including a storage capacitor and access transistor, wherein;   the body bias voltage is different from a power supply voltage of the DRAM cell; and   the transistor is deeply depleted channel (DDC) transistor, the DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region, the screening region having a dopant concentration that is no less than 1×10 18  dopant atoms/cm 3  and that is different from a dopant concentration of a substrate portion or well containing the DDC transistor.