Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips

Abstract

An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.

1 . A method for designing a circuit, comprising:
 converting a circuit having a particular transistor having a channel comprising a plurality of fins configured in parallel into a converted circuit, the converted circuit replacing the particular transistor with a converted transistor having a channel comprising a stacked channel including plurality of stacks arranged in parallel.   
     
     
         2 . The method of  claim 1 , wherein the particular transistor is an n-channel transistor, and the circuit includes in addition a p-channel transistor comprising a second plurality of fins, the second plurality of fins having a different number of fins than the plurality of fins in the particular transistor, and the converted circuit replacing the p-channel transistor with a transistor having a stacked channel comprising a second plurality of stacks arranged in parallel, wherein the stacked channel of the p-channel transistor has as different number of layers than the particular transistor. 
     
     
         3 . The method of  claim 2 , wherein the p-channel transistor has a same number of stacks as the particular transistor. 
     
     
         4 . The method of  claim 1 , including:
 creating a machine readable specification of a cell including the converted circuit; and   storing the machine readable specification in computer readable memory.   
     
     
         5 . The method of  claim 4 , including extracting physical characteristics of the converted circuit, and wherein the machine readable specification includes the extracted physical characteristics. 
     
     
         6 . A method for designing a circuit, comprising:
 converting a circuit having a particular transistor having a channel comprising a plurality of fins configured in parallel into a converted circuit, the converted circuit replacing the particular transistor with a converted transistor having a channel comprising a plurality of stacks of nanowires arranged in parallel.   
     
     
         7 . The method of  claim 6 , wherein the particular transistor is an n-channel transistor, and the circuit includes in addition a p-channel transistor comprising a second plurality of fins, the second plurality of fins having a different number of fins than the plurality of fins in the particular transistor, and the converted circuit replacing the p-channel transistor with a transistor having a channel comprising a second plurality of stacks of nanowires arranged in parallel, wherein the channel of the p-channel transistor has as different number of nanowires than the particular transistor. 
     
     
         8 . The method of  claim 7 , wherein the p-channel transistor has a same number of stacks of nanowires as the particular transistor. 
     
     
         9 . The method of  claim 6 , including:
 creating a machine readable specification of a cell including the converted circuit; and   storing the machine readable specification in computer readable memory.   
     
     
         10 . The method of  claim 9 , including extracting physical characteristics of the converted circuit, and wherein the machine readable specification includes the extracted physical characteristics. 
     
     
         11 . A method for designing a circuit, comprising:
 converting a circuit having a particular transistor having a channel comprising a plurality of fins configured in parallel into a converted circuit, the converted circuit replacing the particular transistor with a converted transistor having a channel comprising a plurality of stacks of 2D material strips arranged in parallel.   
     
     
         12 . The method of  claim 11 , wherein the particular transistor is an n-channel transistor, and the circuit includes in addition a p-channel transistor comprising a second plurality of fins, the second plurality of fins having a different number of fins than the plurality of fins in the particular transistor, and the converted circuit replacing the p-channel transistor with a transistor having a channel comprising a second plurality of stacks of 2D material strips arranged in parallel, wherein the channel of the p-channel transistor has as different number of 2D material strips than the particular transistor. 
     
     
         13 . The method of  claim 12 , wherein the p-channel transistor has a same number of stacks of 2D material strips as the particular transistor. 
     
     
         14 . The method of  claim 11 , including:
 creating a machine readable specification of a cell including the converted circuit; and   storing the machine readable specification in computer readable memory.   
     
     
         15 . The method of  claim 14 , including extracting physical characteristics of the converted circuit, and wherein the machine readable specification includes the extracted physical characteristics.