Contact structure of semiconductor device

Abstract

The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first fin and a second fin over a substrate, the first fin and the second fin having an elongated axis running in a first direction;   an insulation region extending between the first fin and the second fin, the first fin and the second fin extending above the insulation region;   a gate electrode over the insulation region and the first fin and the second fin;   spacers alongside opposing sidewalls of the gate electrode;   a first source/drain region in the first fin and the second fin, the first source/drain region extending laterally away from the gate electrode;   a second source/drain region in the first fin and the second fin, the second source/drain region extending laterally away from the gate electrode;   a first contact structure to the first source/drain region, the first contact structure extending from laterally above the first fin to laterally above the second fin, wherein the first contact structure is spaced apart from a first closest sidewall of the gate electrode by a first distance, the first source/drain region having a uniform dopant concentration from a first spacer of the spacers to the first contact structure; and   a second contact structure to the second source/drain region, the second contact structure extending from laterally above the first fin to laterally above the second fin, wherein the second contact structure is spaced apart from a second closest sidewall of the gate electrode by a second distance, the second distance less than the first distance, the second source/drain region having a uniform dopant concentration from a second spacer of the spacers to the second contact structure.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a semiconductor layer over the first fin and the second fin, wherein the first source/drain region and the second source/drain region comprise the semiconductor layer. 
     
     
         3 . The semiconductor device of  claim 2 , wherein an upper surface of the semiconductor layer is higher than a lower surface of the spacers. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first contact structure is a drain contact and the second contact structure is a source contact. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a ratio of the first distance to the second distance is from about 1.1 to about 5. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a gate bottom surface and the first contact structure comprises a first bottom surface higher than the gate bottom surface. 
     
     
         7 . The semiconductor device of  claim 6 , wherein a first height between the first bottom surface and the gate bottom surface is in a range of about 1 nm to about 50 nm. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a gate bottom surface and the second contact structure comprises a second bottom surface higher than the gate bottom surface. 
     
     
         9 . The semiconductor device of  claim 8 , wherein a second height between the second bottom surface and the gate bottom surface is in a range of about 1 nm to about 50 nm. 
     
     
         10 . A semiconductor device comprising:
 a first fin and a second fin;   an insulation region interposed between the first fin and the second fin;   a gate electrode over channel portions of the first fin and the second fin, the gate electrode extending over a portion of the insulation region;   a semiconductor layer over the first fin and the second fin on opposing sides of the gate electrode, the semiconductor layer extending between the first fin and the second fin;   a first source/drain region and a second source/drain region in the semiconductor layer, the first source/drain region and the second source/drain region on opposing sides of the gate electrode;   an inter-layer dielectric (ILD) layer over the semiconductor layer; and   a first contact extending through the ILD layer to the first source/drain region and a second contact extending through the ILD layer to the second source/drain region, wherein a first distance between a middle of the first contact and a gate of the gate electrode is less than a second distance between a middle of the second contact and the middle of the gate electrode, the first source/drain region having a uniform dopant profile from the first contact to a first gate spacer, the second source/drain region having a uniform dopant profile from the second contact to a second gate spacer.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the first contact is a source contact and the second contact is a drain contact. 
     
     
         12 . The semiconductor device of  claim 10 , wherein a ratio of the second distance to the first distance is from about 1.1 to about 5. 
     
     
         13 . The semiconductor device of  claim 10 , wherein a lattice constant of the semiconductor layer is different than a lattice constant of the first fin and the second fin. 
     
     
         14 . The semiconductor device of  claim 10 , further comprising a semiconductor capping layer over the first fin and the second fin. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the semiconductor capping layer comprises a silicon capping layer. 
     
     
         16 . A method of forming a semiconductor device, the method comprising:
 forming a first fin and a second fin;   forming an insulation region interposed between the first fin and the second fin;   forming a gate electrode over channel portions of the first fin and the second fin, the gate electrode extending over a portion of the insulation region;   forming a semiconductor layer over the first fin and the second fin on opposing sides of the gate electrode, the semiconductor layer extending between the first fin and the second fin;   forming a first source/drain region and a second source/drain region in the semiconductor layer on opposing sides of the gate electrode;   forming an inter-layer dielectric (ILD) layer over the semiconductor layer;   forming a first opening extending through the ILD layer to the first source/drain region and a second opening extending through the ILD layer to the second source/drain region; and   forming a first contact in the first opening and a second contact in the second opening, wherein a first distance between a middle of the first contact and a gate of the gate electrode is less than a second distance between a middle of the second contact and the middle of the gate electrode, the first source/drain region having a uniform dopant profile from the first contact to a first gate spacer, the second source/drain region having a uniform dopant profile from the second contact to a second gate spacer.   
     
     
         17 . The method of  claim 16 , wherein a ratio of the second distance to the first distance is from about 1.1 to about 5. 
     
     
         18 . The method of  claim 16 , wherein forming the semiconductor layer comprises epitaxially growing a strained material over the first fin and the second fin after forming the gate electrode, the strained material extending over the insulation region, wherein a lattice constant of the strained material is different from a lattice constant of the first fin and the second fin. 
     
     
         19 . The method of  claim 18 , wherein the strained material is separated from the gate electrode by a gate spacer. 
     
     
         20 . The method of  claim 16 , wherein forming the first contact comprises forming the first contact such that the first contact overlaps at least a portion of the first fin and the second fin.