Fin cut for tight fin pitch by two different sit hard mask materials on fin

Abstract

Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired SIT spacers are exposed by the cut mask due to the different etching characteristics of the different materials.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a first set of semiconductor fins having a first pitch located in a first region of a substrate; and   a second set of semiconductor fins having a first pitch located in a second region of the substrate,   wherein an outermost semiconductor fin in the second set of semiconductor fins and an adjacent outermost semiconductor fin in the first set of semiconductor fins has a second pitch that is at least 3n times the first pitch, wherein n is an integer greater than 0.   
     
     
         2 . The semiconductor structure of  claim 1 , the second pitch is 3 times the first pitch. 
     
     
         3 . The semiconductor structure of  claim 1 , the second pitch is 6 times the first pitch. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein each of the semiconductor fins in the first set has a width the same as each of the semiconductor fins in the second set. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein each of the semiconductor fins in the first set and the semiconductor fins in the second set has a width ranging from 5 to 10 nm. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the first pitch is from 10 to 50 nm. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the semiconductor fins in the first set and the semiconductor fins in the second set are oriented parallel to one another. 
     
     
         8 . The semiconductor structure of  claim 1 , further comprising a third set of semiconductor fins having the first pitch located in a third region of the substrate adjacent to the second region, wherein an outermost semiconductor fin in the third set of semiconductor fins and an adjacent outermost semiconductor fin in the second set of semiconductor fins has a third pitch that is at least 3n times the first pitch, wherein n is an integer greater than 0. 
     
     
         9 . The semiconductor structure of  claim 8 , wherein the second pitch is 6 times the first pitch, and the third pitch is 3 times the first pitch. 
     
     
         10 . The semiconductor structure of  claim 8 , wherein each of the semiconductor fins in the third set has a width the same as each of the semiconductor fins in the first set and the semiconductor fins in the second set. 
     
     
         11 . The semiconductor structure of  claim 8 , wherein the semiconductor fins in the first set, the semiconductor fins in the second set and the semiconductor fins in the third set are oriented parallel to one another. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein the substrate comprises a handle substrate and an insulator layer overlying the handle substrate. 
     
     
         13 . The semiconductor structure of  claim 12 , wherein the handle substrate comprises a semiconductor material, a conductive material or a dielectric material. 
     
     
         14 . The semiconductor structure of  claim 12 , wherein the insulator layer comprises silicon oxide.