Memory-network processor with programmable optimizations

Abstract

In some embodiments, an apparatus includes processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus. In some embodiments the apparatus includes front-end circuitry configured to retrieve a plurality of instructions for execution and, based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. In some embodiments, this may reduce power consumption by the apparatus.

What is claimed is: 
     
         1 . An apparatus, comprising:
 processing circuitry that includes a plurality of different components configured to perform operations to generate execution results for instructions executed by the apparatus;   front-end circuitry configured to:
 retrieve a plurality of instructions for execution; and 
 based on identification of one or more instruction characteristics of the plurality of instructions, selectively disable one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the one or more instruction characteristics include a repeated instruction sequence. 
     
     
         3 . The apparatus of  claim 2 , wherein the apparatus is configured to store the entire repeated instruction sequence in a buffer during execution. 
     
     
         4 . The apparatus of  claim 2 , wherein the one or more portions are identified as unused for execution of the repeated instruction sequence. 
     
     
         5 . The apparatus of  claim 1 , wherein the one or more portions include a store unit. 
     
     
         6 . The apparatus of  claim 1 , wherein the one or more portions include an address generator unit. 
     
     
         7 . The apparatus of  claim 1 , wherein the one or more portions include a fetch unit. 
     
     
         8 . The apparatus of  claim 1 , wherein the one or more portions include one or more pipeline units. 
     
     
         9 . The apparatus of  claim 1 , wherein to selectively disable the one or more portions, the apparatus is configured to control the one or more portions to enter a low power mode. 
     
     
         10 . The apparatus of  claim 1 , wherein the one or more instructions characteristics are indicated by one or more predicate flags. 
     
     
         11 . A method, comprising:
 performing, by processing circuitry, operations to generate execution results for executed instructions, including:   retrieving, by front-end circuitry, a plurality of instructions for execution; and   selectively disabling, by the front-end circuitry based on identification of one or more instruction characteristics of the plurality of instructions, one or more portions of the processing circuitry for one or more cycles during execution of the plurality of instructions.   
     
     
         12 . The method of  claim 11 , wherein the one or more instruction characteristics include a repeated instruction sequence. 
     
     
         13 . The method of  claim 12 , further comprising storing the entire repeated instruction sequence in a buffer during execution. 
     
     
         14 . The method of  claim 12 , further comprising identifying the one or more portions as unused for execution of the repeated instruction sequence. 
     
     
         15 . The method of  claim 11 , wherein the one or more portions include a store unit. 
     
     
         16 . The method of  claim 11 , wherein the one or more portions include an address generator unit. 
     
     
         17 . The method of  claim 11 , wherein the one or more portions include a fetch unit. 
     
     
         18 . The method of  claim 11 , wherein the one or more portions include one or more pipeline units. 
     
     
         19 . The method of  claim 11 , wherein the selectively disabling is performed by controlling the one or more portions to enter a low power mode. 
     
     
         20 . The method of  claim 11 , wherein the one or more instructions characteristics are indicated by one or more predicate flags.