Mems-based cantilever energy harvester

Abstract

The claimed invention is directed to integrated energy-harvesting piezoelectric cantilevers. The cantilevers are fabricated using sol-gel processing using a sacrificial poly-Si seeding layer. Improvements in film microstructure and electrical properties are realized by introducing a poly-Si seeding layer and by optimizing the poling process.

What is claimed is: 
     
         1 . A piezoelectric energy harvester comprising:
 a cantilever comprising a PZT-PZN or PZT layer, the cantilever secured to a base layer comprising a silicon substrate via a sacrificial layer comprising an isotropically etchable material   
     
     
         2 . The piezoelectric energy harvester of  claim 1 , wherein the cantilever further comprises a silicon oxide layer. 
     
     
         3 . The piezoelectric energy harvester of  claim 1 , wherein the cantilever further comprises a silicon nitride layer. 
     
     
         4 . The piezoelectric energy harvester of  claim 1 , wherein the cantilever further comprises a PECVD silicon oxide layer. 
     
     
         5 . The piezoelectric energy harvester of  claim 1 , wherein the cantilever further comprises a titanium oxide layer. 
     
     
         6 . The piezoelectric energy harvester of  claim 1 , wherein the cantilever further comprises lead titanate. 
     
     
         7 . The piezoelectric energy harvester of  claim 1 , wherein the isotropically etchable material comprises poly-silicon. 
     
     
         8 . The piezoelectric energy harvester of  claim 1 , wherein the sacrificial layer can withstand thermal treatments of at least 600° C. 
     
     
         9 . The piezoelectric energy harvester of  claim 1 , wherein the sacrificial layer is made of a material that is suitable for growth of a large grain PZT-based piezoelectric thin-film. 
     
     
         10 . The piezoelectric energy harvester of  claim 1 , wherein the sacrificial layer is capable of being istropically removed using a liquid chemistry that is selective for a poly-silicon sacrificial layer and is compatible with materials that comprise the cantilever. 
     
     
         11 . The piezoelectric energy harvester of  claim 1 , wherein the sacrificial layer is compatible with a silicon CMOS process flow. 
     
     
         12 . A method for fabricating a piezoelectric energy harvester comprising:
 depositing a poly-silicon layer on a silicon substrate;   depositing a first silicon oxide layer above the poly-silicon layer;   depositing a silicon nitride layer above the first silicon oxide layer; and   depositing a second silicon oxide layer above the silicon nitride layer.   
     
     
         13 . The method of  claim 12 , further comprising depositing, prior to the depositing the first silicon oxide layer, a layer of titanium above the poly-silicon layer. 
     
     
         14 . The method of  claim 13 , wherein the titanium layer is deposited using a sputtering process that is followed by a first thermal treatment. 
     
     
         15 . The method of  claim 14 , wherein the first thermal treatment is carried out at 1,000° C. in air. 
     
     
         16 . The method of  claim 13 , further comprising depositing, before depositing the first silicon oxide layer, a lead titanate layer above the titanium layer. 
     
     
         17 . The method of  claim 16 , wherein the lead titanate layer is deposited using a sol-gel process based on lead (IV) acetate, titanium isopropoxide, acetic acid, and methanol, and wherein the sol-gel process is followed by a second thermal treatment. 
     
     
         18 . The method of  claim 17 , wherein the second thermal treatment is carried out at 675° C. in air. 
     
     
         19 . The method of  claim 16 , further comprising depositing a PZT or a PZT-PZN layer above the second silicon oxide layer. 
     
     
         20 . The method of  claim 19 , further comprising encapsulating the PZT or the PZT-PZN layer with PECVD oxide. 
     
     
         21 . The method of  claim 19 , further comprising depositing Cr and Au layers above the PZT or the PZT-PZN layer for wire bonding. 
     
     
         22 . The method of  claim 19 , further comprising:
 using a first mask to pattern interdigited electrodes via a lift-off process;   using a second mask to encapsulate the piezoelectric energy harvester with Silicon Oxide;   using a third mask to deposit Au pad an end of the piezoelectric energy harvester and at contact electrodes; and   using a fourth mask to define a pattern for wet etch of the piezoelectric energy harvester to form a cantilever disposed over a silicon base layer.   
     
     
         23 . The method of  claim 22 , wherein using the fourth mask further comprises:
 aligning the fourth mask over the piezoelectric energy harvester;   spincoating a photoresist onto the piezoelectric energy harvester;   baking the photoresist;   developing the photoresist;   descumming the piezoelectric energy harvester using reactive-ion-etching; and   baking the photoresist.   
     
     
         24 . The method of  claim 23 , further comprising:
 wet etching the PZT or PZT-PZN layer;   dry etching the silicon nitride layer and the second silicon oxide layer; and   wet etching the poly-silicon layer to separate a portion of the cantilever from the silicon substrate.   
     
     
         25 . The method of  claim 24 , wherein the wet etching of the PZT or PZT-PZN layer uses hydrofluoric acid. 
     
     
         26 . The method of  claim 24 , wherein the wet etching of the poly-silicon layer is done isotropically with potassium hydroxide. 
     
     
         27 . The method of  claim 24 , further comprising depositing a ruthenium oxide layer onto the piezoelectric energy harvester.