Semiconductor Devices and Methods for Forming a Semiconductor Device

Abstract

A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.

What is claimed is: 
     
         1 . A semiconductor device, comprising an electrical device and an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device, wherein the output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device. 
     
     
         2 . The semiconductor device of  claim 1 , wherein the electrical device comprises a switchable electrical structure implemented on a semiconductor die, wherein the semiconductor die comprises a first doping region of a first conductivity type within a semiconductor substrate, wherein the first doping region is arranged within the semiconductor substrate so that the first doping region floats during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure until a depletion zone reaches the first doping region, wherein at least a part of free charge carriers existing within the first doping region are removed from the first doping region as soon as the depletion zone reaches the first doping region. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the semiconductor substrate comprises a cell region laterally surrounded by an edge termination region, wherein the first doping region is located within the edge termination region. 
     
     
         4 . The semiconductor device of  claim 3 , wherein a maximal operating voltage difference applied to the semiconductor device during normal operation occurs between a region of the cell region and an edge of the semiconductor substrate, wherein the semiconductor substrate comprises the first doping region located at an area within the edge termination region comprising between 10% and 90% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device. 
     
     
         5 . The semiconductor device of  claim 2 , wherein the semiconductor die comprises a feedback path configured to enable a reflow of charge carriers during transition from the off-state of the switchable electrical structure to the on-state of the switchable electrical structure, wherein the feedback path is configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the feedback path comprises a second doping region of the first conductivity type configured to be depleted before the depletion zone reaches the first doping region. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the feedback path comprises a diode structure configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the output capacitance characteristic comprises a hysteresis loop portion with different output capacitances for increasing voltage and decreasing voltage. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the output capacitance characteristic comprises a second output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device, wherein the second output capacitance maximum is larger than 1.2 times the output capacitance at the output capacitance minimum located at a voltage between the voltage at the first output capacitance maximum and 5% of a breakdown voltage of the semiconductor device. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the electrical device is a power semiconductor arrangement of a semiconductor die, wherein the power semiconductor arrangement has the output capacitance characteristic. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the power semiconductor transistor arrangement is a vertical power semiconductor transistor arrangement. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the semiconductor die comprises a first connection interface connected to a gate structure of the power semiconductor transistor arrangement, a second connection interface connected to a source structure of the power semiconductor transistor arrangement and a third connection interface connected to a drain structure of the power semiconductor transistor arrangement. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the output capacitance characteristic represents one of a drain-source capacitance between the second connection interface and the third connection interface of the power semiconductor transistor arrangement, a gate-drain capacitance between the first connection interface and the third connection interface of the power semiconductor transistor arrangement or a sum of the drain-source capacitance of the power semiconductor transistor arrangement and the gate-drain capacitance of the power semiconductor transistor arrangement. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the power semiconductor transistor arrangement comprises a plurality of cell compensation regions extending into a semiconductor substrate within a cell region of the semiconductor substrate, wherein one or more drift regions are located adjacent to the plurality of cell compensation regions separating neighboring cell compensation regions of the plurality of cell compensation regions from each other, wherein the cell compensation regions of the plurality of cell compensation regions comprise the first conductivity type and the one or more drift regions comprise the second conductivity type. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the cell compensation regions comprise a laterally summed number of dopants per unit area of the first conductivity type deviating from a laterally summed number of dopants per unit area of the second conductivity type comprised by the one or more drift region by less than +/−25% of the laterally summed number of dopants per unit area of the first conductivity type comprised by the cell compensation regions within the cell region. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the power semiconductor transistor arrangement comprises a first doping region of the first conductivity type within an edge termination region of the semiconductor substrate, wherein the first doping region comprises a number of doping atoms larger than 10 times a number of doping atoms within one cell compensation region of the plurality of cell compensation regions. 
     
     
         17 . A semiconductor device, comprising a switchable electrical structure implemented on a semiconductor die, wherein the semiconductor die comprises:
 a first doping region of a first conductivity type within a semiconductor substrate, wherein the first doping region is arranged within the semiconductor substrate so that the first doping region floats during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure until a depletion zone reaches the first doping region, wherein at least a part of free charge carriers existing within the first doping region are removed from the first doping region as soon as the depletion zone reaches the first doping region; and   a feedback path configured to enable a reflow of charge carriers during transition from the off-state of the switchable electrical structure to the on-state of the switchable electrical structure, wherein the feedback path is configured to block a flow of charge carriers through the feedback path during at least a part of the transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure.   
     
     
         18 . A semiconductor device, comprising a semiconductor substrate comprising a cell region laterally surrounded by an edge termination region, wherein the edge termination region is configured to support a maximal operating voltage difference applied to the semiconductor device during normal operation between the cell region and an edge of the semiconductor substrate, wherein the semiconductor substrate comprises a first doping region located at an area within the edge termination region comprising between 20% and 80% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device, wherein the first doping region is electrically connected by an electrically conductive structure inside or outside the semiconductor substrate to a capacitance increasing structure located within a region of the edge termination region comprising a voltage difference of at least 90% of the maximal operating voltage difference to a region within the cell region. 
     
     
         19 . The semiconductor device of  claim 18 , wherein a structure formed by the first doping region, the capacitance increasing structure and the electrically conductive structure is electrically floating. 
     
     
         20 . The semiconductor device of  claim 18 , wherein the capacitance increasing structure is implemented by at least one second doping region comprising a conductivity type opposite to a conductivity type of semiconductor material of the semiconductor substrate surrounding the at least one second doping region or is implemented by at least one trench filled with electrically conductive material electrically insulated from the semiconductor substrate by an insulation layer within the trench.