US2016322369A1PendingUtilityA1

Nonvolatile semiconductor memory device

Assignee: TOSHIBA KKPriority: Oct 17, 2013Filed: Jul 8, 2016Published: Nov 3, 2016
Est. expiryOct 17, 2033(~7.2 yrs left)· nominal 20-yr term from priority
H01L 27/11524H01L 27/11582G11C 16/26H01L 27/11556G11C 16/0466G11C 16/0408H01L 27/1157H10B 41/35H10B 43/35H10B 41/27H10B 43/27G11C 8/14G11C 5/063
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Claims

Abstract

A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns, and a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns. The first memory connection portion is formed in a first layer of the substrate and the second memory connection portion is formed in a second layer of the substrate that is lower than the first layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A nonvolatile semiconductor memory device comprising:
 first and second word line groups, each including a plurality of stacked word lines above a substrate having first and second layers that are insulated from each other;   a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns; and   a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns, wherein   the first memory connection portion is formed in the first layer of the substrate and the second memory connection portion is formed in the second layer of the substrate that is lower than the first layer.

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