Gate electrode and gate contact plug layouts for integrated circuit field effect transistors

Abstract

A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

1 .- 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 an isolation region in a substrate that defines an active region, the active region extending along first and second different directions;   a common source region of four transistors that extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region;   four drain regions, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region; and   four gate electrodes, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions, a respective gate electrode including a first extending portion and a second extending portion, a respective first extending portion extending from an end of a respective second extending portion and extending along the first direction, a respective second extending portion extending along the second direction, and a respective first extending portion including a first part and a second part; and   four gate contact plugs, a respective one of which is electrically connected to a respective one of the four gate electrodes, a first pair of which are connected to a respective one of a first pair of the gate electrodes on the first parts thereof, and a second pair of which are connected to a respective one of a second pair of the gate electrodes on the second parts thereof,   wherein the first pair of the four gate contact plugs are substantially symmetric with respect to a first virtual straight line which passes through the center of the active region and extends along the second direction; and   the second pair of the four gate contact plugs are substantially symmetric with respect to the first virtual straight line.   
     
     
         22 . The semiconductor device according to  claim 21  wherein a respective one of the second pair of the four gate contact plugs is offset from a second virtual straight line which passes through a center of a respective one of the first pair of the four gate contact plugs and extends along the second direction. 
     
     
         23 . The semiconductor device according to  claim 21  wherein the first pair of the gate electrodes and the second pair of the gate electrodes are substantially symmetric with respect to a second virtual straight line which passes through the center of the active region and extends along the first direction. 
     
     
         24 . The semiconductor device according to  claim 21  wherein a respective gate electrode further includes a third extending portion that extends from the other end of a respective second extending portion and extends along the first direction,
 a respective third extending portion includes a third part and a fourth part; and 
 the four gate contact plugs are four first gate contact plugs, 
 the semiconductor device further comprising four second gate contact plugs, a respective one of which is electrically connected to a respective one of the four gate electrodes, a first pair of which are connected to a respective one of the first pair of the gate electrodes on the third parts thereof, and a second pair of which are connected to a respective one of the second pair of the gate electrodes on the fourth parts thereof; 
 
     
     
         25 . The semiconductor device according to  claim 24  wherein one of the first gate contact plugs and one of the second gate contact plugs, which are on one of the first pair of the gate electrodes, are substantially aligned in the second direction 
     
     
         26 . The semiconductor device according to  claim 21  further comprising:
 a source contact plug electrically connected to the common source region; and 
 four drain contact plugs, a respective one of which is electrically connected to a respective one of the four drain regions. 
 
     
     
         27 . A semiconductor device comprising:
 an active region of a substrate, the active region including a common source region of four transistors, the common source region including a first portion extending along the first direction and a second portion extending along the second direction, the first and second portions crossing each other at a center of the active region to define four quadrants of the active region that are outside the common source region;   first to fourth gate electrodes in the four quadrants, respectively, a set of the first and second gate electrodes and a set of the third and fourth gate electrodes being substantially symmetric with respect to the first portion of the common source region, and a set of the first and third gate electrodes and a set of the second and fourth gate electrodes being substantially symmetric with respect to the second portion of the common source region,   wherein first and second gate contact plugs are electrically connected to the first gate electrode, the first and second gate contact plugs are substantially aligned with a first virtual straight line which passes through centers of the first and second gate contact plugs and extends along the second direction; and   third and fourth gate contact plugs are electronically connected to the third gate electrode, the third and fourth gate contact plugs are offset from the first virtual straight line.   
     
     
         28 . The semiconductor device according to  claim 27  wherein a respective gate electrode includes first to third extending portions;
 a respective first extending portion extends from an end of a respective second extending portion and extends along the first direction; 
 a respective third extending portion extends from the other end of a respective second extending portion and extends along the first direction; 
 a respective second extending portion extends along the second direction; 
 the first and third gate contact plugs are disposed on the first extending portions of the first and third gate electrodes, respectively; and 
 the second and fourth gate contact plugs are disposed on the third extending portions of the first and third gate electrodes, respectively. 
 
     
     
         29 . The semiconductor device according to  claim 27  wherein a set of the first and second gate contact plugs and a set of the third and fourth gate contact plugs are asymmetric with respect to the first portion of the common source region. 
     
     
         30 . The semiconductor device according to  claim 27  further comprising:
 fifth and sixth gate contact plugs electrically connected to the second gate electrode, the fifth and sixth gate contact plugs being substantially aligned with a second virtual straight line which passes through centers of the fifth and sixth gate contact plugs and extends along the second direction; and 
 seventh and eighth gate contact plugs electronically connected to the fourth gate electrode, the seventh and eighth gate contact plugs being offset from the second virtual straight line. 
 
     
     
         31 . The semiconductor device according to  claim 30  wherein a set of the first to fourth gate contact plugs and a set of the fifth to eighth gate contact plugs are substantially symmetric with respect to the second portion of the common source region. 
     
     
         32 . The semiconductor device according to  claim 27  further comprising first to fourth drain regions in the four quadrants, respectively,
 wherein a respective drain region is spaced apart from the common source region with a respective gate electrode interposed therebetween. 
 
     
     
         33 . A semiconductor device comprising:
 an active region of a substrate, the active region including a common source region of four transistors, the common source region including a first portion extending along the first direction and a second portion extending along the second direction, the first and second portions crossing each other at a center of the active region to define four quadrants of the active region that are outside the common source region;   first to fourth gate electrodes in the four quadrants, respectively; and   a first pair of gate contact plugs, a second pair of gate contact plugs, a third of gate contact plugs and a fourth of gate contact plugs that are electrically connected to the first to fourth gate electrodes, respectively,   wherein a first structure including the first gate electrode and the first pair of gate contact plugs and a second structure including the second gate electrode and the second pair of gate contact plugs are substantially symmetric with respect to the second portion of the common source region;   a third structure including the third gate electrode and the third pair of gate contact plugs and a fourth structure including the fourth gate electrode and the fourth pair of gate contact plugs are substantially symmetric with respect to the second portion of the common source region; and   the first pair of gate contact plugs and the third pair of gate contact plugs are asymmetric with respect to the first portion of the common source region.   
     
     
         34 . The semiconductor device according to  claim 33  wherein the first pair of gate contact plugs are substantially aligned in the second direction; and
 the second pair of gate contact plugs are substantially aligned in the second direction. 
 
     
     
         35 . The semiconductor device according to  claim 33  wherein one of the third pair of gate contact plugs is offset from a virtual straight line which passes through a center of the other of the third pair of gate contact plugs and extends along the first direction 
     
     
         36 . The semiconductor device according to  claim 33  wherein a respective gate electrode includes a pair of extending portions that extend along the first direction; and
 the pair of gate contact plugs are respectively on the pair of extending portions of a respective gate electrode. 
 
     
     
         37 . The semiconductor device according to  claim 33  wherein the second pair of gate contact plugs and the fourth pair of gate contact plugs are asymmetric with respect to the first portion of the common source region. 
     
     
         38 . The semiconductor device according to  claim 33  further comprising first to fourth drain regions in the four quadrants, respectively,
 wherein a respective drain region is spaced apart from the common source region with a respective gate electrode interposed therebetween.