Semiconductor device and manufacturing method of the same

Abstract

According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first semiconductor layer;   a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region;   an interlayer insulation film covering the first semiconductor layer and the plurality of first transistors;   a first conductor provided in the interlayer insulation film and electrically connected to the first diffusion region;   a second semiconductor layer provided on the interlayer insulation film;   a plurality of second transistors including a plurality of second gate structures provided on the second semiconductor layer, a second channel region provided in the second semiconductor layer and under the second gate structure, and a plurality of second diffusion regions provided in the second semiconductor layer in a manner to sandwich the second channel region; and   a second conductor provided in a through-hole penetrating the second semiconductor layer, and electrically connected to the first conductor and the second diffusion region,   wherein the second diffusion region is provided also on an inner wall of the through-hole penetrating the second semiconductor layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the second semiconductor layer is silicon (Si), polysilicon (poly-Si), amorphous silicon (a-Si), germanium (Ge), polygermanium (poly-Ge), amorphous germanium (a-Ge), germanium tin (GeSn), polygermanium tin (poly-GeSn), amorphous germanium tin (a-GeSn), or a compound thereof. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the second semiconductor layer is gallium arsenic (GaAs), indium gallium arsenic (InGaAs), indium arsenic (InAs), indium phosphorus (InP), indium antimony (InSb), indium gallium phosphorus (InGaP), gallium antimony (GaSb), gallium phosphorus (GaP), or a compound thereof. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the second semiconductor layer is an oxide semiconductor of zinc oxide (ZnO) or indium gallium zinc oxide (InGaZnO). 
     
     
         5 . The semiconductor device of  claim 1 , wherein a conductive film including a metal is provided between the second conductor and the first conductor, and between the second conductor and the second diffusion region. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the second diffusion layer and the second conductor are formed of mutually different materials. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the second diffusion region is a semiconductor-metal compound. 
     
     
         8 . A semiconductor device comprising:
 a first semiconductor layer;   a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region;   an interlayer insulation film covering the first semiconductor layer and the plurality of first transistors;   a second semiconductor layer provided on the interlayer insulation film;   a plurality of second transistors including a plurality of second gate structures provided on the second semiconductor layer, a second channel region provided in the second semiconductor layer and under the second gate structure, and a plurality of second diffusion regions provided in a manner to extend from a top surface to a back surface of the second semiconductor layer and in a manner to sandwich the second channel region; and   a first conductor provided in the interlayer insulation film, and electrically connected to the first diffusion region and the second diffusion region on the back surface of the second semiconductor layer.   
     
     
         9 . A manufacturing method of a semiconductor device, comprising:
 a step of forming gate structures of a plurality of first transistors on a first semiconductor layer;   a step of forming a plurality of first diffusion regions in the first semiconductor layer, where the gate structures of the first transistors are not formed;   a step of forming an interlayer insulation film covering the first semiconductor layer and the plurality of first transistors;   a step of forming a first conductor in the interlayer insulation film, the first conductor being electrically connected to the first diffusion region;   a step of forming a second semiconductor layer on the interlayer insulation film and on the first conductor;   a step of forming a region, which becomes an active region, in the second semiconductor layer, and forming a through-hole, which penetrates the second semiconductor layer, on the first conductor;   a step of forming gate structures of a plurality of second transistors on the second semiconductor layer;   a step of forming a plurality of second diffusion regions in the second semiconductor layer, where the gate structures of the second transistors are not formed, and forming a third diffusion region on an inner wall of the through-hole penetrating the second semiconductor layer; and   a step of forming a second conductor which is formed in the through-hole and is electrically connected to the first conductor and the third diffusion region.   
     
     
         10 . The manufacturing method of a semiconductor device of  claim 9 , wherein the step of forming the second diffusion region and the third diffusion region includes:
 a step of forming a metallic film on the second semiconductor layer, where the second transistor is not formed, and in the through-hole; and   a step of forming a metal compound film by reacting the metallic film and the second semiconductor layer.   
     
     
         11 . The manufacturing method of a semiconductor device of  claim 10 , wherein the step of forming the metal compound film is carried out by anneal at temperatures of less than 500° C. 
     
     
         12 . The manufacturing method of a semiconductor device of  claim 9 , wherein the second semiconductor layer is silicon (Si), polysilicon (poly-Si), amorphous silicon (a-Si), germanium (Ge), polygermanium (poly-Ge), amorphous germanium (a-Ge), germanium tin (GeSn), polygermanium tin (poly-GeSn), amorphous germanium tin (a-GeSn), or a compound thereof. 
     
     
         13 . The manufacturing method of a semiconductor device of  claim 9 , wherein the second semiconductor layer is gallium arsenic (GaAs), indium gallium arsenic (InGaAs), indium arsenic (InAs), indium phosphorus (InP), indium antimony (InSb), indium gallium phosphorus (InGaP), gallium antimony (GaSb), gallium phosphorus (GaP), or a compound thereof. 
     
     
         14 . The manufacturing method of a semiconductor device of  claim 9 , wherein the step of forming the second diffusion region and the third diffusion region includes:
 a step of removing oxygen in the second semiconductor layer, where the second transistor is not formed, and in the through-hole.   
     
     
         15 . The manufacturing method of a semiconductor device of  claim 9 , wherein the second semiconductor layer is an oxide semiconductor of zinc oxide (ZnO) or indium gallium zinc oxide (InGaZnO).