Techniques for Fabricating Reduced-Line-Edge-Roughness Trenches for Aspect Ratio Trapping

Abstract

The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.

What is claimed is: 
     
         1 . A silicon substrate comprising:
 one or more silicon fins separated from one or more epitaxial III-V semiconductor material fins by an oxide, wherein the epitaxial III-V semiconductor material is selected from the group consisting of: aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium arsenide phosphide, indium gallium nitride, indium nitride, indium phosphide and combinations comprising at least one of the foregoing materials.   
     
     
         2 . The silicon substrate of  claim 1 , wherein the silicon fins and the epitaxial III-V semiconductor material fins are planar. 
     
     
         3 . The silicon substrate of  claim 1 , wherein the oxide comprises spacers along sidewalls of the silicon fins. 
     
     
         4 . The silicon substrate of  claim 1 , wherein the oxide comprises a thermal oxide. 
     
     
         5 . The silicon substrate of  claim 1 , comprising a plurality of the silicon fins and a plurality of the epitaxial III-V semiconductor material fins. 
     
     
         6 . The silicon substrate of  claim 5 , wherein the silicon fins and the epitaxial III-V semiconductor material fins alternate. 
     
     
         7 . The silicon substrate of  claim 6 , wherein each of the silicon fins is separated from an adjacent one of the epitaxial III-V semiconductor material fins by the oxide. 
     
     
         8 . The silicon substrate of  claim 6 , wherein the epitaxial III-V semiconductor material fins are taller than the silicon fins.