Memory systems having reduced memory channel traffic and methods for operating the same

Abstract

A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.

1 . A memory device controller, comprising:
 an error correction processor configured to obtain error location information for page data received from a source memory block over a memory channel; and   a compression processor configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the received page data over the same memory channel.   
     
     
         2 . The memory device controller of  claim 1 , wherein the compression processor is configured to output only the compressed error location information to the target memory block. 
     
     
         3 . The memory device controller of  claim 1 , wherein the error correction processor is further configured to perform error correction coding on the received page data to obtain the error location information for the page data, the error location information including locations of errors in the received page data. 
     
     
         4 . The memory device controller of  claim 1 , wherein the source memory block and the target memory block are located at a same non-volatile memory device connected to the memory channel. 
     
     
         5 . The memory device controller of  claim 1 , wherein the received page data is valid page data read from the source memory block during a garbage collection operation. 
     
     
         6 . The memory device controller of  claim 1 , wherein
 the received page data is on-chip buffered program (OBP) data; and   the compressed error location information is buffered prior to being output to the target memory block.   
     
     
         7 . The memory device controller of  claim 6 , wherein the source memory block and the target memory block are located at a same non-volatile memory device connected to the memory channel. 
     
     
         8 . A storage device comprising:
 a source non-volatile memory device connected to a memory channel, the source non-volatile memory device including a source memory block; and   a memory device controller configured to communicate with the source non-volatile memory device via the memory channel, the memory device controller including,   an error correction processor configured to obtain error location information for page data received from the source memory block over the memory channel; and   a compression processor configured to compress the obtained error location information, and output the compressed error location information to a target memory block without the page data over the same memory channel.   
     
     
         9 . The storage device of  claim 8 , wherein the page data is valid page data read from the source memory block during a garbage collection operation. 
     
     
         10 . The storage device of  claim 8 , wherein
 the page data is on-chip buffered program (OBP) data; and   the compressed error location information is buffered prior to being output to the target memory block.   
     
     
         11 . A storage device comprising:
 a first non-volatile memory device connected to a memory channel, the first non-volatile memory device including a plurality of memory blocks and a page buffer, and the first non-volatile memory device being configured to   buffer page data read from a source memory block,   correct errors in the buffered page data in response to receiving error location information from a memory device controller via the memory channel, and without receiving the page data from the memory device controller, and   write the error corrected page data to a target memory block among the plurality of memory blocks of the first non-volatile memory device.   
     
     
         12 . The storage device of  claim 11 , wherein
 at least one of the source and the target memory blocks are in the form of a three-dimensional memory array.   
     
     
         13 . The storage device of  claim 12 , wherein the three dimensional memory array includes a plurality of memory cells, each of the plurality of memory cells including a charge trap layer. 
     
     
         14 . The storage device of  claim 11 , wherein the first non-volatile memory device is a NAND device. 
     
     
         15 . The storage device of  claim 11 , wherein the first non-volatile memory device is configured to correct errors in the buffered page data in response to receiving only the compressed error location information from the memory device controller. 
     
     
         16 . The storage device of  claim 11 , wherein the first non-volatile memory device further includes the source memory block. 
     
     
         17 . The storage device of  claim 11 , wherein the page data is one of on-chip buffered program (OBP) data and valid page data read from the source memory block during a garbage collection operation. 
     
     
         18 - 20 . (canceled)