System and method for sharing a communications link between multiple communications protocols

Abstract

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

I claim: 
     
         1 . An integrated circuit comprising:
 (a) a test data in lead;   (b) a test data out lead;   (c) a data register path having an input connected to the test data in lead and an output;   (d) an instruction register path having an input connected to the test data in lead and having an output;   (e) a global bypass register having an input connected to the test data in lead and having an output;   (f) a first multiplexer having an input connected to the output of the data register path, an input connected to the output of the instruction register path, a first control input, and a legacy test data output; and   (g) a second multiplexer having an input connected to the output of the global bypass register, an input connected to the legacy test data output, a second control input, and an output.   
     
     
         2 . The integrated circuit of  claim 1  in which the output of the second multiplexer provides one of a legacy test data output and a global bypass output. 
     
     
         3 . The integrated circuit of  claim 1  in which the global bypass register is one bit. 
     
     
         4 . The integrated circuit of  claim 1  including a test access port controller having control leads connected to the instruction register.